1 -------------------------------------------------------
  2 -- Design Name : ram_dp_sr_sw
  3 -- File Name   : ram_dp_sr_sw.vhd
  4 -- Function    : Synchronous read write RAM
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10     use ieee.std_logic_unsigned.all;
 11 
 12 entity ram_dp_sr_sw is
 13     generic (
 14         DATA_WIDTH :integer := 8;
 15         ADDR_WIDTH :integer := 8
 16     );
 17     port (
 18         clk       :in    std_logic;                                -- Clock Input
 19         address_0 :in    std_logic_vector (ADDR_WIDTH-1 downto 0); -- address_0 Input
 20         data_0    :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data_0 bi-directional
 21         cs_0      :in    std_logic;                                -- Chip Select
 22         we_0      :in    std_logic;                                -- Write Enable/Read Enable
 23         oe_0      :in    std_logic;                                -- Output Enable
 24         address_1 :in    std_logic_vector (ADDR_WIDTH-1 downto 0); -- address_1 Input
 25         data_1    :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data_1 bi-directional
 26         cs_1      :in    std_logic;                                -- Chip Select
 27         we_1      :in    std_logic;                                -- Write Enable/Read Enable
 28         oe_1      :in    std_logic                                 -- Output Enable
 29     );
 30 end entity;
 31 architecture rtl of ram_dp_sr_sw is
 32    ----------------Internal variables----------------
 33     constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
 34 
 35     signal data_0_out :std_logic_vector (DATA_WIDTH-1 downto 0);
 36     signal data_1_out :std_logic_vector (DATA_WIDTH-1 downto 0);
 37 
 38     type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
 39     signal mem : RAM (0 to RAM_DEPTH-1);
 40 
 41 begin
 42    ----------------Code Starts Here------------------
 43    -- Memory Write Block
 44    -- Write Operation : When we_0 = 1, cs_0 = 1
 45     MEM_WRITE:
 46     process (clk) begin
 47         if (rising_edge(clk)) then
 48             if ( cs_0 = '1' and we_0 = '1') then
 49                 mem(conv_integer(address_0)) <= data_0;
 50             elsif (cs_1 = '1' and we_1 = '1') then
 51                 mem(conv_integer(address_1)) <= data_1;
 52             end if;
 53         end if;
 54     end process;
 55 
 56    -- Tri-State Buffer control
 57     data_0 <= data_0_out when (cs_0 = '1' and oe_0 = '1' and we_0 = '0') else (others=>'Z');
 58 
 59    -- Memory Read Block
 60     MEM_READ_0:
 61     process (clk) begin
 62         if (rising_edge(clk)) then
 63             if (cs_0 = '1' and we_0 = '0' and oe_0 = '1') then
 64                 data_0_out <= mem(conv_integer(address_0));
 65             else
 66                 data_0_out <= (others=>'0');
 67             end if;
 68         end if;
 69     end process;
 70 
 71    --Second Port of RAM
 72    -- Tri-State Buffer control
 73    -- output : When we_0 = 0, oe_0 = 1, cs_0 = 1
 74     data_1 <= data_1_out when (cs_1 = '1' and oe_1 = '1' and we_1 = '0') else (others=>'Z');
 75 
 76    -- Memory Read Block 1
 77     MEM_READ_1:
 78     process (clk) begin
 79         if (rising_edge(clk)) then
 80             if (cs_1 = '1' and we_1 = '0' and oe_1 = '1') then
 81                 data_1_out <= mem(conv_integer(address_1));
 82             else
 83                 data_1_out <= (others=>'0');
 84             end if;
 85         end if;
 86     end process;
 87 
 88 end architecture;

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