1 -------------------------------------------------------
  2 -- Design Name : cam
  3 -- File Name   : cam.vhd
  4 -- Function    : CAM
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10     use ieee.std_logic_unsigned.all;
 11     use ieee.std_logic_arith.all;
 12 
 13 entity cam is
 14     generic (
 15         ADDR_WIDTH :integer := 8
 16     );
 17     port (
 18         clk         :in  std_logic;-- Cam clock
 19         cam_enable  :in  std_logic;-- Cam enable
 20         cam_data_in :in  std_logic_vector (2**ADDR_WIDTH-1 downto 0);-- Cam data to match
 21         cam_hit_out :out std_logic;-- Cam match has happened
 22         cam_addr_out:out std_logic_vector (ADDR_WIDTH-1 downto 0) -- Cam output address
 23     );
 24 end entity;
 25 architecture rtl of cam is
 26    ----------------Internal variables----------------
 27     constant DEPTH :integer := 2**ADDR_WIDTH;
 28 
 29     signal cam_addr_combo :std_logic_vector (ADDR_WIDTH-1 downto 0);
 30     signal cam_hit_combo  :std_logic;
 31     signal found_match    :std_logic;
 32 begin
 33    ---------------Code Starts Here-------
 34     process (cam_data_in, cam_hit_combo, cam_addr_combo, found_match) begin
 35         cam_addr_combo   <= (others=>'0');
 36         found_match      <= '0';
 37         cam_hit_combo    <= '0';
 38         for i in 0 to DEPTH-1 loop
 39             if (cam_data_in(i) = '1' and found_match = '0') then
 40                 found_match     <= '1';
 41                 cam_hit_combo   <= '1';
 42                 cam_addr_combo  <= conv_std_logic_vector(i, cam_addr_combo'length);
 43             else
 44                 found_match     <= found_match;
 45                 cam_hit_combo   <= cam_hit_combo;
 46                 cam_addr_combo  <= cam_addr_combo;
 47             end if;
 48         end loop;
 49     end process;
 50 
 51    -- register the outputs
 52     process (clk) begin
 53         if (rising_edge(clk)) then
 54             if (cam_enable = '1') then
 55                 cam_hit_out  <= cam_hit_combo;
 56                 cam_addr_out <= cam_addr_combo;
 57             else
 58                 cam_hit_out  <= '0';
 59                 cam_addr_out <= (others=>'0');
 60             end if;
 61         end if;
 62     end process;
 63 
 64 end architecture;

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com