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Asynchronous FIFO
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Note: This code is written in Verilog 2001. |
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1 ------------------------------------------------------------
2 -- Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
3 -- Coder : Alex Claros F.
4 -- Date : 15/May/2005.
5 -- Notes : This implementation is based on the article
6 -- 'Asynchronous FIFO in Virtex-II FPGAs'
7 -- writen by Peter Alfke. This TechXclusive
8 -- article can be downloaded from the
9 -- Xilinx website. It has some minor modifications.
10 -- Coder : Deepak Kumar Tala (Verilog)
11 -- Translator: Alexander H Pham (VHDL)
12 ------------------------------------------------------------
13 library ieee;
14 use ieee.std_logic_1164.all;
15 use ieee.std_logic_unsigned.all;
16
17 entity aFifo is
18 generic (
19 DATA_WIDTH :integer := 8;
20 ADDR_WIDTH :integer := 4
21 );
22 port (
23 -- Reading port.
24 Data_out :out std_logic_vector (DATA_WIDTH-1 downto 0);
25 Empty_out :out std_logic;
26 ReadEn_in :in std_logic;
27 RClk :in std_logic;
28 -- Writing port.
29 Data_in :in std_logic_vector (DATA_WIDTH-1 downto 0);
30 Full_out :out std_logic;
31 WriteEn_in :in std_logic;
32 WClk :in std_logic;
33
34 Clear_in:in std_logic
35 );
36 end entity;
37 architecture rtl of aFifo is
38 ----/Internal connections & variables------
39 constant FIFO_DEPTH :integer := 2**ADDR_WIDTH;
40
41 type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
42 signal Mem : RAM (0 to FIFO_DEPTH-1);
43
44 signal pNextWordToWrite :std_logic_vector (ADDR_WIDTH-1 downto 0);
45 signal pNextWordToRead :std_logic_vector (ADDR_WIDTH-1 downto 0);
46 signal EqualAddresses :std_logic;
47 signal NextWriteAddressEn :std_logic;
48 signal NextReadAddressEn :std_logic;
49 signal Set_Status :std_logic;
50 signal Rst_Status :std_logic;
51 signal Status :std_logic;
52 signal PresetFull :std_logic;
53 signal PresetEmpty :std_logic;
54 signal empty,full :std_logic;
55
56 component GrayCounter is
57 generic (
58 COUNTER_WIDTH :integer := 4
59 );
60 port (
61 GrayCount_out :out std_logic_vector (COUNTER_WIDTH-1 downto 0);
62 Enable_in :in std_logic; --Count enable.
63 Clear_in :in std_logic; --Count reset.
64 clk :in std_logic
65 );
66 end component;
67 begin
68
69 --------------Code--------------/
70 --Data ports logic:
71 --(Uses a dual-port RAM).
72 --'Data_out' logic:
73 process (RClk) begin
74 if (rising_edge(RClk)) then
75 if (ReadEn_in = '1' and empty = '0') then
76 Data_out <= Mem(conv_integer(pNextWordToRead));
77 end if;
78 end if;
79 end process;
80
81 --'Data_in' logic:
82 process (WClk) begin
83 if (rising_edge(WClk)) then
84 if (WriteEn_in = '1' and full = '0') then
85 Mem(conv_integer(pNextWordToWrite)) <= Data_in;
86 end if;
87 end if;
88 end process;
89
90 --Fifo addresses support logic:
91 --'Next Addresses' enable logic:
92 NextWriteAddressEn <= WriteEn_in and (not full);
93 NextReadAddressEn <= ReadEn_in and (not empty);
94
95 --Addreses (Gray counters) logic:
96 GrayCounter_pWr : GrayCounter
97 port map (
98 GrayCount_out => pNextWordToWrite,
99 Enable_in => NextWriteAddressEn,
100 Clear_in => Clear_in,
101 clk => WClk
102 );
103
104 GrayCounter_pRd : GrayCounter
105 port map (
106 GrayCount_out => pNextWordToRead,
107 Enable_in => NextReadAddressEn,
108 Clear_in => Clear_in,
109 clk => RClk
110 );
111
112 --'EqualAddresses' logic:
113 EqualAddresses <= '1' when (pNextWordToWrite = pNextWordToRead) else '0';
114
115 --'Quadrant selectors' logic:
116 process (pNextWordToWrite, pNextWordToRead)
117 variable set_status_bit0 :std_logic;
118 variable set_status_bit1 :std_logic;
119 variable rst_status_bit0 :std_logic;
120 variable rst_status_bit1 :std_logic;
121 begin
122 set_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xnor pNextWordToRead(ADDR_WIDTH-1);
123 set_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xor pNextWordToRead(ADDR_WIDTH-2);
124 Set_Status <= set_status_bit0 and set_status_bit1;
125
126 rst_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xor pNextWordToRead(ADDR_WIDTH-1);
127 rst_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xnor pNextWordToRead(ADDR_WIDTH-2);
128 Rst_Status <= rst_status_bit0 and rst_status_bit1;
129 end process;
130
131 --'Status' latch logic:
132 process (Set_Status, Rst_Status, Clear_in) begin 133 if (Rst_Status = '1' or Clear_in = '1') then
134 Status <= '0'; --Going 'Empty'.
135 elsif (Set_Status = '1') then
136 Status <= '1'; --Going 'Full'.
137 end if;
138 end process;
139
140 --'Full_out' logic for the writing port:
141 PresetFull <= Status and EqualAddresses; --'Full' Fifo.
142
143 process (WClk, PresetFull) begin--D Flip-Flop w/ Asynchronous Preset.
144 if (PresetFull = '1') then
145 full <= '1';
146 elsif (rising_edge(WClk)) then
147 full <= '0';
148 end if;
149 end process;
150 Full_out <= full;
151
152 --'Empty_out' logic for the reading port:
153 PresetEmpty <= not Status and EqualAddresses; --'Empty' Fifo.
154
155 process (RClk, PresetEmpty) begin--D Flip-Flop w/ Asynchronous Preset.
156 if (PresetEmpty = '1') then
157 empty <= '1';
158 elsif (rising_edge(RClk)) then
159 empty <= '0';
160 end if;
161 end process;
162
163 Empty_out <= empty;
164 end architecture;
You could download file vhdl_examples here
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1 ----------------------------------------
2 -- Function : Code Gray counter.
3 -- Coder : Alex Claros F.
4 -- Date : 15/May/2005.
5 -- Translator : Alexander H Pham (VHDL)
6 ----------------------------------------
7 library ieee;
8 use ieee.std_logic_1164.all;
9 use ieee.std_logic_unsigned.all;
10 use ieee.std_logic_arith.all;
11
12 entity GrayCounter is
13 generic (
14 COUNTER_WIDTH :integer := 4
15 );
16 port ( --'Gray' code count output.
17 GrayCount_out :out std_logic_vector (COUNTER_WIDTH-1 downto 0);
18 Enable_in :in std_logic; -- Count enable.
19 Clear_in :in std_logic; -- Count reset.
20 clk :in std_logic -- Input clock
21 );
22 end entity;
23
24 architecture rtl of GrayCounter is
25 signal BinaryCount :std_logic_vector (COUNTER_WIDTH-1 downto 0);
26 begin
27 process (clk) begin
28 if (rising_edge(clk)) then
29 if (Clear_in = '1') then
30 --Gray count begins @ '1' with
31 BinaryCount <= conv_std_logic_vector(1, COUNTER_WIDTH);
32 GrayCount_out <= (others=>'0');
33 -- first 'Enable_in'.
34 elsif (Enable_in = '1') then
35 BinaryCount <= BinaryCount + 1;
36 GrayCount_out <= (BinaryCount(COUNTER_WIDTH-1) &
37 BinaryCount(COUNTER_WIDTH-2 downto 0) xor
38 BinaryCount(COUNTER_WIDTH-1 downto 1));
39 end if;
40 end if;
41 end process;
42
43 end architecture;
You could download file vhdl_examples here
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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