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  ../../images/main/bulllet_4dots_orange.gif Interface File
   

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  1 `ifndef MEM_PORTS_SV
  2 `define MEM_PORTS_SV
  3 
  4 interface mem_ports(
  5  input  wire  clock,
  6  output logic [7:0] address,
  7  output logic chip_en,
  8  output logic read_write,
  9  output logic [7:0] data_in,
 10  input logic [7:0] data_out
 11 );
 12 endinterface
 13 
 14 `endif
You could download file sv_examples here
   

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Deepak Kumar Tala - All rights reserved

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