1 module memory(
  2 address,
  3 data_in,
  4 data_out,
  5 read_write,
  6 chip_en
  7 );
  8 
  9 input wire [7:0] address, data_in;
 10 output reg [7:0] data_out;
 11 input wire read_write, chip_en;
 12 
 13 reg [7:0] mem [0:255];
 14 
 15 always @ (address or data_in or read_write or chip_en)
 16 if (read_write == 1 && chip_en == 1) begin
 17   mem[address] = data_in;
 18 end
 19 
 20 always @ (read_write or chip_en or address)
 21 if (read_write == 0 && chip_en) 
 22   data_out = mem[address];
 23 else
 24   data_out = 0;
 25 
 26 endmodule

  1 `include "memory.sv"
  2 
  3 module memory_tb();
  4 
  5 wire [7:0] address, data_in;
  6 wire [7:0] data_out;
  7 wire  read_write, chip_en;
  8 reg clk;
  9 
 10 // Connect the interface
 11 mem_ports ports(
 12  .clock       (clk),
 13  .address     (address),
 14  .chip_en     (chip_en),
 15  .read_write  (read_write),
 16  .data_in     (data_in),
 17  .data_out    (data_out)
 18 );
 19 
 20 // Connect the program
 21 memory_top top (ports);
 22 
 23 initial begin
 24   clk = 0;
 25 end	
 26 
 27 always  #1  clk = ~clk;
 28 
 29 memory U_memory(
 30 .address             (address),
 31 .data_in             (data_in),
 32 .data_out            (data_out),
 33 .read_write          (read_write),
 34 .chip_en             (chip_en)
 35 );
 36 endmodule

  1 
  2 `include "mem_ports.sv"
  3 
  4 program memory_top(mem_ports ports);
  5 `include "mem_base_object.sv"
  6 `include "mem_driver.sv"
  7 `include "mem_txgen.sv"
  8 `include "mem_scoreboard.sv"
  9 `include "mem_ip_monitor.sv"
 10 `include "mem_op_monitor.sv"
 11   mem_txgen txgen;
 12   mem_scoreboard sb;
 13   mem_ip_monitor ipm;
 14   mem_op_monitor opm;
 15 
 16 initial begin
 17   sb    = new();
 18   ipm   = new (sb, ports);
 19   opm   = new (sb, ports);
 20   txgen = new(ports);
 21   fork
 22     ipm.input_monitor();
 23     opm.output_monitor();
 24   join_none
 25   txgen.gen_cmds();
 26   repeat (20) @ (posedge ports.clock);
 27 end
 28 
 29 endprogram

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

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