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Gray Counter
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1 //-----------------------------------------------------
2 // Design Name : gray_counter
3 // File Name : gray_counter.sv
4 // Function : 8 bit gray counter
5 // Coder : Deepak
6 //-----------------------------------------------------
7 module gray_counter (
8 output wire [7:0] out , // counter out
9 input wire enable , // enable for counter
10 input wire clk , // clock
11 input wire rst // active hight reset
12 );
13 //------------Internal Variables--------
14 reg [7:0] count;
15 //-------------Code Starts Here---------
16 always_ff @ (posedge clk)
17 if (rst) begin
18 count <= 0;
19 end else if (enable) begin
20 count <= count + 1;
21 end
22
23 assign out = { count[7], (count[7] ^ count[6]),(count[6] ^
24 count[5]),(count[5] ^ count[4]), (count[4] ^
25 count[3]),(count[3] ^ count[2]), (count[2] ^
26 count[1]),(count[1] ^ count[0]) };
27
28 endmodule
You could download file sv_examples here
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Copyright © 1998-2025 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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