1 //-----------------------------------------------------
  2 // Design Name : clk_div_45
  3 // File Name   : clk_div_45.sv
  4 // Function    : Divide by 4.5
  5 // Coder      : Deepak
  6 //-----------------------------------------------------
  7 module clk_div_45 (
  8 input  wire clk_in, // Input Clock
  9 input  wire enable, // Enable is sync with falling edge of clk_in
 10 output wire clk_out // Output Clock
 11 );
 12 //--------------Internal Registers----------------------
 13 reg   [3:0] counter2   ;
 14 reg   [3:0] counter2   ;
 15 reg         toggle1    ;
 16 reg         toggle2    ;
 17 
 18 //--------------Code Starts Here-----------------------
 19 always @ (posedge clk_in)
 20 if (enable == 1'b0) begin 
 21    counter1 <= 4'b0;
 22    toggle1  <= 0;
 23 end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4))  begin
 24    counter1 <= 4'b0;
 25    toggle1  <= ~toggle1;
 26 end else   begin
 27    counter1 <= counter1 + 1;
 28 end
 29    
 30 always @ (negedge clk_in)
 31 if (enable == 1'b0) begin
 32   counter2 <= 4'b0;
 33   toggle2  <= 0;
 34 end else if ((counter2 == 3 && ~toggle2) || (toggle2 && counter2 == 4))  begin
 35   counter2 <= 4'b0;
 36   toggle2  <= ~toggle2;
 37 end  else   begin
 38   counter2 <= counter2 + 1;
 39 end
 40 
 41 assign  clk_out = (counter1 <3 && counter2 < 3) & enable;
 42 
 43 endmodule

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Deepak Kumar Tala - All rights reserved

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