1 //-----------------------------------------------------
  2 // Design Name : divide_by_3 
  3 // File Name   : divide_by_3.sv
  4 // Function    : Divide By 3
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module divide_by_3 (
  8 input   wire   clk_in       , //Input Clock
  9 input   wire   reset        , // Reset Input
 10 output  wire   clk_out        // Output Clock
 11 );
 12 //------------Internal Variables--------
 13 reg [1:0] pos_cnt;
 14 reg [1:0] neg_cnt;
 15 //-------------Code Start-----------------
 16 // Posedge counter
 17 always_ff @ (posedge clk_in)
 18 if (reset) begin
 19   pos_cnt <= 0;
 20 end else begin
 21   pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1;
 22 end
 23 // Neg edge counter
 24 always_ff @ (negedge clk_in)
 25 if (reset) begin
 26   neg_cnt <= 0;
 27 end else begin
 28   neg_cnt <= (neg_cnt == 2) ? 0 : neg_cnt + 1;
 29 end
 30 
 31 assign clk_out = ((pos_cnt  ! = 2) && (neg_cnt  ! = 2));
 32 
 33 endmodule

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