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  ../images/main/bullet_green_ball.gif VHDL Reserved Words
   

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Keyword

Meaning

abs

operator, absolute value of right operand. No () needed.

access

used to define an access type, pointer

after

specifies a time after NOW

alias

create another name for an existing identifier

all

dereferences what precedes the .all

and

operator, logical "and" of left and right operands

architecture

a secondary design unit

array

used to define an array, vector or matrix

assert

used to have a program check on itself

attribute

used to declare attribute functions

begin

start of a begin end pair

block

start of a block structure

body

designates a procedure body rather than declaration

buffer

a mode of a signal, holds a value

bus

a mode of a signal, can have multiple drivers

case

part of a case statement

component

starts the definition of a component

configuration

a primary design unit

constant

declares an identifier to be read only

disconnect

signal driver condition

downto

middle of a range 31 downto 0

else

part of "if" statement, if cond then ... else ... end if;

elsif

part of "if" statement, if cond then ... elsif cond ...

end

part of many statements, may be followed by word and id

entity

a primary design unit

exit

sequential statement, used in loops

file

used to declare a file type

for

start of a for type loop statement

function

starts declaration and body of a function

generate

make copies, possibly using a parameter

generic

introduces generic part of a declaration

group

collection of types that can get an attribute

guarded

causes a wait until a signal changes from False to True

if

used in "if" statements

impure

an impure function is assumed to have side effects

in

indicates a parameter in only input, not changed

inertial

signal characteristic, holds a value

inout

indicates a parameter is used and computed in and out

is

used as a connective in various statements

label

used in attribute statement as entity specification

library

context clause, designates a simple library name

linkage

a mode for a port, used like buffer and inout

literal

used in attribute statement as entity specification

loop

sequential statement, loop ... end loop;

map

used to map actual parameters, as in port map

mod

operator, left operand modulo right operand

nand

operator, "nand" of left and right operands

new

allocates memory and returns access pointer

next

sequential statement, used in loops

nor

operator, "nor" of left and right operands

not

operator, complement of right operand

null

sequential statement and a value

of

used in type declarations, of Real ;

on

used as a connective in various statements

open

initial file characteristic

or

operator, logical "or" of left and right operands

others

fill in missing, possibly all, data

out

indicates a parameter is computed and output

package

a design unit, also package body

port

interface definition, also port map

postponed

make process wait for all non postponed process to suspend

procedure

typical programming procedure

process

sequential or concurrent code to be executed

pure

a pure function may not have side effects

range

used in type definitions, range 1 to 10;

record

used to define a new record type

register

signal parameter modifier

reject

clause in delay mechanism, followed be a time

rem

operator, remainder of left operand divided by right op

report

statement and clause in assert statement, string output

return

statement in procedure or function

rol

operator, left operand rotated left by right operand

ror

operator, left operand rotated right by right operand

select

used in selected signal assignment statement

severity

used in assertion and reporting, followed by a severity

signal

declaration that an object is a signal

shared

used to declare shared objects

sla

operator, left operand shifted left arithmetic by right op

sll

operator, left operand shifted left logical by right op

sra

operator, left operand shifted right arithmetic by right

srl

operator, left operand shifted right logical by right op

subtype

declaration to restrict an existing type

then

part of if condition then ...

to

middle of a range 1 to 10

transport

signal characteristic

type

declaration to create a new type

unaffected

used in signal waveform

units

used to define new types of units

until

used in wait statement

use

make a package available to this design unit

variable

declaration that an object is a variable

wait

sequential statement, also used in case statement

when

used for choices in case and other statements

while

kind of loop statement

with

used in selected signal assignment statement

xnor

operator, exclusive "nor" of left and right operands

xor

operator, exclusive "or" of left and right operands

   

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  ../images/main/bullet_green_ball.gif VHDL Operators
   

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Highest precedence first, left to right within same precedence group, use parenthesis to control order. Unary operators take an operand on the right. "result same" means the result is the same as the right operand. Binary operators take an operand on the left and right. "result same" means the result is the same as the left operand.

   

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**

exponentiation

numeric ** integer

result numeric

abs

absolute value

abs numeric

result numeric

not

complement

not logic or boolean

result same

*

multiplication

numeric * numeric

result numeric

/

division

numeric / numeric

result numeric

mod

modulo

integer mod integer

result integer

rem

remainder

integer rem integer

result integer

+

unary plus

+ numeric

result numeric

-

unary minus

- numeric

result numeric

+

addition

numeric + numeric

result numeric

-

subtraction

numeric - numeric

result numeric

&

concatenation

array or element & array or element

result array

sll

shift left logical

logical array sll integer

result same

srl

shift right logical

logical array srl integer

result same

sla

shift left arithmetic

logical array sla integer

result same

sra

shift right arithmetic

logical array sra integer

result same

rol

rotate left

logical array rol integer

result same

ror

rotate right

logical array ror integer

result same

=

test for equality

result is boolean

/=

test for inequality

result is boolean

<

test for less than

result is boolean

<=

test for less than or equal

result is boolean

>

test for greater than

result is boolean

>=

test for greater than or equal

result is boolean

and

logical and

logical array or boolean

result is same

or

logical or

logical array or boolean

result is same

nand

logical complement of and

logical array or boolean

result is same

nor

logical complement of or

logical array or boolean

result is same

xor

logical exclusive or

logical array or boolean

result is same

xnor

logical complement of exclusive or

logical array or boolean

result is same

   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com