quick.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

   

space.gif

   

space.gif

  ../images/main/bullet_green_ball.gif Introduction

VHDL stands for VHSIC Hardware Description Language, and VHSIC in turn stands for Very High Speed Integrated Circuits. VHDL is an acronym for Very High Speed Integrated Circuit Hardware Description Language which is a programming language used to describe a logic circuit by function, data flow behaviour, or structure.

   

space.gif

VHDL is a programming language: although VHDL was not designed for writing general purpose programs, you can write any algorithm with the VHDL language. If you are able to write programs, you will find in VHDL features similar to those found in procedural languages such as C, Pascal or Ada. VHDL derives most of its syntax and semantics from Ada. Knowing Ada is an advantage for learning VHDL (it is an advantage in general as well).

   

space.gif

However, VHDL was not designed as a general purpose language but as an HDL (hardware description language). As the name implies, VHDL aims at modeling or documenting electronics systems. Due to the nature of hardware components which are always running, VHDL is a highly concurrent language, built upon an event-based timing model.

   

space.gif

Like a program written in any other language, a VHDL program can be executed. Since VHDL is used to model designs, the term simulation is often used instead of execution, with the same meaning.

   

space.gif

Like a program written in another hardware description language, a VHDL program can be transformed with a synthesis tool into a netlist, that is, a detailed gate-level implementation.

   

space.gif

../images/verilog/d_ff.gif
   

space.gif


  1 library ieee;
  2 use ieee.std_logic_1164.all;
  3 
  4 entity d_ff is
  5 port 	(d, clk   : in std_logic;
  6 	 q, q_bar : out std_logic);
  7 end entity d_ff;
  8 
  9 architecture behav of d_ff is
 10 begin
 11   state_change : process (clk) is
 12   begin
 13     if clk'event and clk = '1' then
 14       q <= d;
 15       q_bar <= not d;
 16     end if;
 17   end process state_change;
 18 end architecture behave;
You could download file d_ff.vhd here
   

space.gif

One can describe a simple Flip flop as that in above figure as well as one can describe a complicated designs having 1 million gates. VHDL is one of the HDL languages available in the industry for designing the Hardware. VHDL allows us to design a Digital design at Behavior Level, Register Transfer Level (RTL), Gate level and at switch level. VHDL allows hardware designers to express their designs with behavioral constructs, deferring the details of implementation to a later stage of design in the final design.

   

space.gif

Many engineers who want to learn VHDL, most often ask this question, how much time it will take to learn VHDL?, Well my answer to them is "It may not take more than one week, if you happen to know at least one programming language".

   

space.gif

  ../images/main/bullet_green_ball.gif Design Styles

VHDL like any other hardware description language, permits the designers to design a design in either Bottom-up or Top-down methodology.

   

space.gif

  ../images/main/bulllet_4dots_orange.gif Bottom-Up Design

The traditional method of electronic design is bottom-up. Each design is performed at the gate-level using the standard gates ( Refer to the Digital Section for more details) With increasing complexity of new designs this approach is nearly impossible to maintain. New systems consist of ASIC or microprocessors with a complexity of thousands of transistors. These traditional bottom-up designs have to give way to new structural, hierarchical design methods. Without these new design practices it would be impossible to handle the new complexity.

   

space.gif

  ../images/main/bulllet_4dots_orange.gif Top-Down Design

The desired design-style of all designers is the top-down design. A real top-down design allows early testing, easy change of different technologies, a structured system design and offers many other advantages. But it is very difficult to follow a pure top-down design. Due to this fact most designs are mix of both the methods, implementing some key elements of both design styles.

   

space.gif

   

space.gif

  ../images/main/bullet_star_pink.gif Figure shows a Top-Down design approach.
   

space.gif

../images/verilog/design_flow.gif
   

space.gif

  ../images/main/bullet_green_ball.gif Abstraction Levels of VHDL

VHDL supports a design at many different levels of abstraction. Three of them are very important:

   

space.gif

  • Behavioral level
  • Register-Transfer Level
  • Gate Level
   

space.gif

  ../images/main/bulllet_4dots_orange.gif Behavioral level

This level describes a system by concurrent algorithms (Behavioral). Each algorithm itself is sequential, that means it consists of a set of instructions that are executed one after the other. Functions, Tasks and Always blocks are the main elements. There is no regard to the structural realization of the design.

   

space.gif

  ../images/main/bulllet_4dots_orange.gif Register-Transfer Level

Designs using the Register-Transfer Level specify the characteristics of a circuit by operations and the transfer of data between the registers. An explicit clock is used. RTL design contains exact timing possibility, operations are scheduled to occur at certain times. Modern definition of a RTL code is "Any code that is synthesizable is called RTL code".

   

space.gif

  ../images/main/bulllet_4dots_orange.gif Gate Level

Within the logic level the characteristics of a system are described by logical links and their timing properties. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`). The usable operations are predefined logic primitives (AND, OR, NOT etc gates). Using gate level modeling might not be a good idea for any level of logic design. Gate level code is generated by tools like synthesis tools and this netlist is used for gate level simulation and for backend.

   

space.gif

   

space.gif

   

space.gif

   

space.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

  

Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com