To demonstrate a random generator of Specman, lets consider a simple memory, which needs address, data and read/write command to memory.

  1 // This Examples shows how random 
  2 // Test vectors is generated
  3 
  4 // This is base object
  5 class m_base_o {
  6   rand bit [7:0] addr ;
  7   rand bit [7:0] data ;
  8   rand bit       rd_wr;
  9 
 10   constraint c1 {
 11     addr > 0;
 12     data > 0;
 13   }
 14 
 15   task print() {
 16     printf ("-------------------------\n");
 17     printf ("Address : %x\n",addr);
 18     printf ("Data    : %x\n",data);
 19     printf ("Write   : %x\n",rd_wr);
 20  }
 21 }
 22 
 23 // This is transcation generator
 24 class txgen {
 25   m_base_o base_ob;
 26   integer num_cmds;
 27   integer i,s;
 28 
 29   // Method to generate commands
 30   task gen_tx () {
 31      base_ob = new();
 32     // Generate num_cmds commands
 33     for ( i = 0; i < num_cmds; i ++) {
 34       s = base_ob.randomize();
 35       base_ob.print();
 36     }
 37   }
 38 }
 39 
 40 // Top level for any vera testbench
 41 program memory {
 42    txgen tx;
 43    tx = new();
 44    tx.num_cmds = 5;
 45    tx.gen_tx();
 46 }

Memory example can be simulating with following command

vcs -ntb -R memory.vr

Output of VERA is as given below.

 -------------------------
 Address : 06
 Data    : 58
 Write   : 1
 -------------------------
 Address : 31
 Data    : 03
 Write   : 1
 -------------------------
 Address : f3
 Data    : d5
 Write   : 0
 -------------------------
 Address : 31
 Data    : 03
 Write   : 0
 -------------------------
 Address : 1a
 Data    : 5b
 Write   : 1

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com