A virtual port is a user-defined data type that contains a set of port signal members grouped together under a given user-defined port name.

Syntax

port virtual_port_name{ port_signal_member_name1; ... port_signal_member_nameN; }

Tasks and functions, therefore, can be defined with reference to port signal members, instead of specific interface signals, which enables reuse of these tasks and functions.

There can, of course, be multiple port variables of the same virtual port type. The port signal members of each virtual port variable can be assigned to different sets of interface signals, respectively. When a task or function is called and a virtual port variable is passed as an argument, operations are performed on the set of interface signals that are assigned to the port signal members.

  1 #include "vera_defines.vrh"
  2 
  3 // Port Declaration
  4 port count_p {
  5   clock;
  6   reset;
  7   enable;
  8   cout;
  9 }
 10 // This is what connects with HDL
 11 interface count_if0 {
 12  input clock      CLOCK;
 13  output reset     PHOLD#1;
 14  output enable    PHOLD#1;
 15  input [3:0] cout PSAMPLE #-1;
 16 }
 17 // Now bind interface with Port
 18 bind count_p count_bind {
 19   clock  count_if0.clock;
 20   reset  count_if0.reset;
 21   enable count_if0.enable;
 22   cout   count_if0.cout;
 23 }
 24 // Top level program 
 25 program virtual_port {
 26    count_p count = count_bind;
 27    // Start the actual test here
 28    @ (posedge count.$clock);
 29    printf("Asserting Reset\n");
 30    count.$reset = 1;
 31    count.$enable = 0;
 32    @ (posedge count.$clock);
 33    printf("Deasserting Reset\n");
 34    count.$reset = 0;
 35    @ (posedge count.$clock);
 36    printf("Asserting Enable\n");
 37    count.$enable = 1;
 38    repeat(10) {
 39      @ (posedge count.$clock);
 40      printf("Counter value %x\n",count.$cout);
 41    }
 42    @ (posedge count.$clock);
 43    printf("Deasserting Enable\n");
 44    count.$enable = 0;
 45 }

  1 module virtual_port_verilog ();
  2 // Internal variables
  3 reg [3:0] counter;
  4 reg       clk;
  5 wire      rst;
  6 wire      counter_en;
  7 // Connect the program here
  8 virtual_port vshell(
  9  .SystemClock (clk),
 10  .\count_if0.clock       (clk),
 11  .\count_if0.reset       (rst),
 12  .\count_if0.enable      (counter_en),
 13  .\count_if0.cout        (counter)
 14 );
 15 // Init all the variables
 16 initial begin
 17   clk = 0;
 18 end
 19 // Clock generator
 20 always  #1  clk = ~clk;
 21 // Counter code
 22 always @ (posedge clk)
 23   if (rst) counter <= 0;
 24   else if (counter_en) counter <= counter + 1;
 25 
 26 endmodule

vcs -ntb -ntb_define SYNOPSYS_NTB +define+SYNOPSYS_NTB virtual_port.vr virtual_port.v -R

 Asserting Reset
 Deasserting Reset
 Asserting Enable
 Counter value 00
 Counter value 01
 Counter value 02
 Counter value 03
 Counter value 04
 Counter value 05
 Counter value 06
 Counter value 07
 Counter value 08
 Counter value 09
 Deasserting Enable

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Deepak Kumar Tala - All rights reserved

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