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  ../images/main/bulllet_4dots_orange.gif m_state

Use the m_state state declaration to declare multiple state bins up to a maximum of 4096 bins.

   

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The syntax is:

   

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m_state state_bin_name (exp1:exp2);

   

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  • state_bin_name : is the base name of the state bins being created.
  • exp : can be any valid coverage expression. You cannot call functions in the expressions, but the expressions can include variables.

When you use the m_state declaration, Vera creates multiple state bins covering all the values in the range and evaluates expressions when the coverage object is instantiated.

   

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  ../images/main/bullet_star_pink.gif Example
   

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  1 class coverage_m_state {
  2   bit [3:0] value;
  3   integer   now;
  4 
  5   coverage_group something {
  6      sample_event = wait_var(now);
  7      sample value {
  8        m_state ABC_ (0:12);
  9      }
 10   }
 11 
 12   task new () {
 13     now = 0;
 14   }
 15 
 16   task update_coverage (bit [3:0] value) {
 17      this.value = value;
 18      now ++;
 19   }
 20 }
 21 
 22 
 23 
 24 program test {
 25   coverage_m_state cov = new();
 26   bit [3:0] v; 
 27   repeat (10) {
 28     v = random();
 29     printf("Value is %d\n",v);
 30     cov.update_coverage(v);
 31     delay(1);
 32   }
 33 }    
You could download file coverage_m_state.vr here
   

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  ../images/main/bullet_star_pink.gif Simulation log
   

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 Value is 12
 Value is 13
 Value is 15
 Value is  9
 Value is 13
 Value is 10
 Value is  6
 Value is  3
 Value is 15
 Value is  5
   

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  ../images/main/bullet_star_pink.gif Coverage Report
   

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 Group : test::coverage_m_state::something
 
 ====================================================
 Group : test::coverage_m_state::something
 ====================================================
 Score   Weight  Goal    
  46.15  1       100     
 
 
 
 
 ====================================================
 
 Samples for Group : test::coverage_m_state::something
 
 
 
 Variable Expected Covered Percent Goal Weight 
                                               
 Total    13       6       46.15               
                                               
 value    13       6       46.15   100  1      
                                               
 
 
 ====================================================
 
 Summary for variable value
 
 
                   Expected Covered Percent 
                                            
 User Defined Bins 13       6       46.15   
                                            
 
 
 User Defined Bins for value
 
 
 Uncovered bins
 
 name    count at least  
                        
 ABC__0  0     1        
                        
 ABC__1  0     1        
                        
 ABC__2  0     1        
                        
 ABC__4  0     1        
                        
 ABC__7  0     1        
                        
 ABC__8  0     1        
                        
 ABC__11 0     1        
                        
 
 
 Covered bins
 
 name    count at least  
                        
 ABC__3  1     1        
                        
 ABC__5  1     1        
                        
 ABC__6  1     1        
                        
 ABC__9  1     1        
                        
 ABC__10 1     1        
                        
 ABC__12 1     1        
                        
 
 
   

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Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com