In last few pages we saw how to contraint a random variable to legal range that we want to generate. In next few pages we will see.

• default constraint
• inclusive and exclusive
• distribution
• conditional constraint
• foreach
• solve before hard

And also some advanced constraint topics.

Default constraints are like soft constraints in other HVL. What I mean by default constraint is, Vera randomizer first applies Default contraints before applying other contraints in the class.

Any constraint that is applied while executing default constraint can be overridden with normal constraints. Below example shows how default constraint works in Vera.

  1 class frame_t {
  2   rand bit start_bit;
  3   rand bit [7:0] data;
  4   bit parity;
  5   rand bit stop_bit;
  6 
  7   default constraint valid{
  8     start_bit == 0;
  9     stop_bit == 1;
 10   }
 11 
 12   constraint framing_error {
 13     start_bit == 1;
 14     stop_bit == 0;
 15   }
 16 
 17   task post_randomize() {
 18     parity = ^data;
 19   }
 20 
 21   task new() {
 22     integer i = this.constraint_mode(OFF,"framing_error");
 23   }
 24 }
 25 
 26 program default_constraint {
 27    frame_t frame = new();
 28    integer i = 0;
 29    // Print frame before randomize
 30    printf("-------------------------------\n");
 31    frame.object_print(); 
 32    printf("-------------------------------\n");
 33    i = frame.randomize(); 
 34    frame.object_print(); 
 35    printf("-------------------------------\n");
 36    i = frame.constraint_mode(ON,"framing_error");
 37    i = frame.randomize() with {
 38       data == 7;
 39    };
 40    frame.object_print(); 
 41    printf("-------------------------------\n");
 42    
 43 }

 -------------------------------
     start_bit           : bin: x
     data                : bin: xxxxxxxx
     parity              : bin: x
     stop_bit            : bin: x
 -------------------------------
     start_bit           : hex: 0
     data                : hex: 36
     parity              : hex: 0
     stop_bit            : hex: 1
 -------------------------------
     start_bit           : hex: 1
     data                : hex: 07
     parity              : hex: 1
     stop_bit            : hex: 0
 -------------------------------

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com