All About Reset

All About Reset

Synchronous Reset : Reset is sampled with respect to clock

Asynchronous Reset : Reset is sampled with no respect to clock.

Synchronous Reset	Asynchronous Reset
Synchronous reset requires more gates to implement (see the example below)	Asynchronous reset requires less gates to implement (see the example below)
Synchronous reset requires clock to be active always	Asynchronous reset does not require clock to be always active
Synchronous reset does not have metastability problems.	Asynchronous reset suffer from metastability problems.
Synchronous reset is slow.	Asynchronous reset is fast.

Code Example

Synchronous Reset


  1 module syn_reset (clk,reset,a,c);
  2    input clk;
  3    input reset;
  4    input a; 
  5    output c; 
  6 
  7    wire clk;
  8    wire reset;   
  9    wire a;   
 10    reg c;
 11   
 12 always @ (posedge clk )
 13   if ( reset == 1'b1) begin
 14     c <= 0;
 15   end else begin
 16     c <= a;
 17   end
 18  
 19 endmodule

You could download file syn_reset.v here

Asynchronous Reset


  1 module  asyn_reset(clk,reset,a,c);
  2      input clk;
  3      input reset;
  4      input a;
  5      output c; 
  6 
  7    wire clk;
  8    wire reset;   
  9    wire a;    
 10    reg c;
 11         
 12 always @ (posedge clk or posedge reset)
 13  if ( reset == 1'b1) begin
 14    c <= 0;
 15  end else begin
 16    c <= a;
 17  end
 18 endmodule

You could download file asyn_reset.v here

Synthesis Output

Synchronize the asynchronous external reset signal, use this synchronous reset as input to all the asynchronous flip-flops inside the design, as shown in the figure below. We do this as an asynchronous reset flip-flop takes less logic to implement, is faster, consumes less power.

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