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  ../images/main/bullet_green_ball.gif Introduction

VMM stands for Verification Methodology Manual. This was developed by Synopsys. I think this is one of the best verification methodology out there. Ofcourse we have RVM, which is same as VMM, but it is for VERA. VMM was developed based on RVM and improved upon RVM.

   

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Before VMM came, each verification engineer use to write verification env in his own way, there was no standard way to define BFM, checkers, base objects. Even in same company and same projects, there was variations in how testbenches were written. It was difficult for other engineers to understand other engineers testbench and thus resulting in poor reuse.

   

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VMM what it does is, it defines a framework of how things should be done, it saves lot of typing, and all the testbenches looks same.

   

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../images/systemverilog/vmm.png
   

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Following are important components of VMM class library

   

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  • vmm_log :Common messaging class
  • vmm_data :This is used for modelling data units or base objects.
  • vmm_xactor :This is used for modelling BFM, checkers, anything that requires threads
  • vmm_channel :This is like FIFO, which can used for passing data from one object to another object.
  • vmm_notify :This is event notification class.
  • vmm_atomic_gen :This is random vmm_data generator for generating random stimulus.
  • vmm_scenario_gen :This is used for generating array of random vmm_data for creating complex random stimulus.
  • vmm_env :This is top level testbench, which sequences various operation in testbench.
   

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When you write testbench using vmm, vmm.sv file should be included and when compiling with vmm in VCS following command line options should be passed in addition to what you already pass

   

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-ntb_opts rvm

   

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For other simulators you can always point to the VMM library path with +incdir compile option

   

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Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com