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Pass by name
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SystemVerilog allows arguments to tasks and functions to be passed by name as well as by position. This is same as module port connection by port name. We can mix postion and name while calling a function/task, as long as order of declaration and order of passing arguments are same. |
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Example - Pass by name
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1 module function_by_name ();
2
3 reg [7:0] data ;
4 reg parity_out;
5
6 time ltime;
7
8 function automatic reg parity (ref reg [7:0] idata, ref time itime);
9 parity = 0;
10 for (int i= 0; i < 8; i ++) begin
11 parity = parity ^ idata[i];
12 end
13 // We can modify the data passed through reference
14 idata ++ ;
15 // Something that is passed as const ref, can not be modified
16 // tdata ++ ; This is wrong
17 endfunction
18
19 initial begin
20 parity_out = 0;
21 data = 0;
22 for (int i=250; i<256; i ++) begin
23 #5 data = i;
24 ltime = $time;
25 // By Name
26 parity_out = parity (.idata(data), .itime(ltime));
27 // By position and name
28 parity_out = parity (data, .itime(ltime));
29 // This is wrong, by name should not be before position
30 //parity_out = parity (.idata(data), ltime);
31 $display ("Data = %00000000b, Parity = %b, Modified data : %b",
32 i, parity_out, data);
33 end
34 #10 $finish;
35 end
36
37 endmodule
You could download file function_by_name.sv here
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Simulation Output
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Data = 11111010, Parity = 1, Modified data : 11111100
Data = 11111011, Parity = 0, Modified data : 11111101
Data = 11111100, Parity = 1, Modified data : 11111110
Data = 11111101, Parity = 1, Modified data : 11111111
Data = 11111110, Parity = 0, Modified data : 00000000
Data = 11111111, Parity = 0, Modified data : 00000001
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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