The solver must assure that the random values are selected to give a uniform value distribution over legal value combinations. To assist with above, SystemVerilog provides feature called solve before.

This is kind of similar to what we have in E language (i.e gen before).

  1 program ordering;
  2   class frame_t;
  3     rand bit zero;
  4     rand bit [15:0] data [];
  5   
  6     constraint frame_sizes {
  7       solve zero before data.size;
  8       zero -> data.size == 0;
  9       data.size inside {[0:10]};
 10       foreach (data[i])
 11         data[i] == i;
 12 
 13     }
 14     function void post_randomize();
 15       begin
 16         $display("length   : %0d", data.size());
 17         for (integer i = 0; i < data.size(); i++) begin
 18          $write ("%2x ",data[i]);
 19         end
 20         $write("\n");
 21       end
 22     endfunction
 23   endclass
 24 
 25   initial begin
 26      frame_t frame = new();
 27      integer i,j = 0;
 28      for (j=0;j < 4; j++) begin
 29        $write("-------------------------------\n");
 30        $write("Randomize Value\n");
 31        i = frame.randomize();
 32      end
 33      $write("-------------------------------\n");
 34   end
 35 
 36 endprogram

 -------------------------------
 Randomize Value
 length   : 2
 00 01 
 -------------------------------
 Randomize Value
 length   : 0
 
 -------------------------------
 Randomize Value
 length   : 0
 
 -------------------------------
 Randomize Value
 length   : 5
 00 01 02 03 04 
 -------------------------------

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