The SystemVerilog operators are a combination of Verilog and C operators. In both languages, the type and size of the operands is fixed, and hence the operator is of a fixed type and size. The fixed type and size of operators is preserved in SystemVerilog.

In addition to the simple assignment operator, =, SystemVerilog includes the C assignment operators and special bitwise assignment operators:

• +=
• -=
• *=
• /=
• %=
• &=
• |=
• ^=
• <<=
• >>=
• <<<=
• >>>=

An assignment operator is semantically equivalent to a blocking assignment, with the exception that any left hand side index expression is only evaluated once.

assignment_operator ::= = | += | -= | *= | /= | %= | &= | |= | ^= 
  | <<= | >>= | <<<= | >>>=
conditional_expression ::= cond_predicate ? { attribute_instance } 
  expression : expression
unary_operator ::= + | - | ! | ~ | & | ~& | | | ~| | ^ | ~^ | ^~
binary_operator ::= + | - | * | / | % | == | != | === | !== | =?= | 
  !?= | && | || | ** | < | <= | > | >= | & 
   | | | ^ | ^~ | ~^ | >> | << | >>> | <<<
inc_or_dec_operator ::= ++ | --
unary_module_path_operator ::= ! | ~ | & | ~& | | | ~| | ^ | ~^ | ^~
binary_module_path_operator ::= == | != | && | || | & | | | ^ | ^~ | ~^

  1 module assignment_operator ();
  2 
  3 reg [31:0] a = 100;
  4 
  5 initial begin
  6   $display (" a         := %h",  a );  
  7   a += 4; 
  8   $display (" a += 4    := %h",  a );  
  9   a -= 4; 
 10   $display (" a -= 4    := %h",  a ); 
 11   a *= 4; 
 12   $display (" a *= 4    := %h",  a ); 
 13   a /= 4; 
 14   $display (" a /= 4    := %h",  a ); 
 15   a %= 17; 
 16   $display (" a %s= 17    := %h", "%", a ); 
 17   a &= 16'hFFFF; 
 18   $display (" a &= 16'hFFFF    := %h",  a ); 
 19   a |= 16'hFFFF; 
 20   $display (" a |= 16'hFFFF    := %h",  a ); 
 21   a ^= 16'hAAAA; 
 22   $display (" a ^= 16h'AAAA    := %h",  a ); 
 23   a <<= 4; 
 24   $display (" a <<= 4   := %h",  a ); 
 25   a >>= 4; 
 26   $display (" a >>= 4   := %h",  a ); 
 27   a <<<= 14; 
 28   $display (" a <<<= 14  := %h",  a ); 
 29   a >>>= 14; 
 30   $display (" a >>>= 14  := %h",  a );
 31    #1  $finish;
 32 end
 33 
 34 endmodule

  a         := 00000064
  a += 4    := 00000068
  a -= 4    := 00000064
  a *= 4    := 00000190
  a /= 4    := 00000064
  a %= 17    := 0000000f
  a &= 16'hFFFF    := 0000000f
  a |= 16'hFFFF    := 0000ffff
  a ^= 16h'AAAA    := 00005555
  a <<= 4   := 00055550
  a >>= 4   := 00005555
  a <<<= 14  := 15554000
  a >>>= 14  := 00005555

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com