Interface definitions can take advantage of parameters and parameter redefinition, in the same manner as module definitions. There is no difference between parameters used in a module and a interface.

Below example shows usage of prameter inside a interface.

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 // Define the interface
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 interface count_if #(WIDTH = 4) (input clk);
  5   logic   reset;
  6   logic   enable;
  7   logic  [WIDTH-1 : 0] count;
  8   //=================================================
  9   // Modports declaration 
 10   //=================================================
 11   modport dut (input clk, reset, enable, output count);
 12   modport tb  (input clk, count, output reset, enable, import monitor);
 13   //=================================================
 14   // Monitor Task
 15   //=================================================
 16   task  monitor();
 17     while (1) begin
 18       @ (posedge clk);
 19       if (enable) begin
 20         $display ("@%0dns reset %b enable %b count %b",
 21           $time, reset, enable, count); 
 22       end
 23     end
 24   endtask
 25 endinterface
 26 //+++++++++++++++++++++++++++++++++++++++++++++++++
 27 // Counter DUT
 28 //+++++++++++++++++++++++++++++++++++++++++++++++++
 29 module counter #(WIDTH = 4) (count_if.dut dif);
 30   //=================================================
 31   // Dut implementation
 32   //=================================================
 33   always @ (posedge dif.clk)
 34     if (dif.reset) begin
 35        dif.count <= {WIDTH{1'b0}};
 36     end else if (dif.enable) begin
 37        dif.count ++;
 38     end
 39 endmodule
 40 //+++++++++++++++++++++++++++++++++++++++++++++++++
 41 // Program for counter (TB)
 42 //+++++++++++++++++++++++++++++++++++++++++++++++++
 43 program counterp #(WIDTH = 4) (count_if.tb tif);
 44   //=================================================
 45   // Default Clocking for using ##<n> delay
 46   //=================================================
 47   default clocking cb @ (posedge tif.clk);
 48 
 49   endclocking
 50   //=================================================
 51   // Generate the test vector
 52   //=================================================
 53   initial begin
 54     // Fork of the monitor
 55     fork
 56       tif.monitor();
 57     join_none
 58     tif.reset <= 1;
 59     tif.enable <= 0;
 60      ##10  tif.reset <= 0;
 61      ##1  tif.enable <= 1;
 62      ##10  tif.enable <= 0;
 63      ##5  $finish;
 64   end
 65 endprogram
 66 //+++++++++++++++++++++++++++++++++++++++++++++++++
 67 // Top Level 
 68 //+++++++++++++++++++++++++++++++++++++++++++++++++
 69 module interface_parameter();
 70   localparam  WIDTH = 5;
 71   logic clk = 0;
 72   always  #1  clk ++;
 73 
 74   count_if #(WIDTH)         cif (clk);
 75   counter  #(.WIDTH(WIDTH)) dut (cif);
 76   counterp #(WIDTH)         tb  (cif);
 77 
 78 endmodule

 @23ns reset 0 enable 1 count 00001
 @25ns reset 0 enable 1 count 00010
 @27ns reset 0 enable 1 count 00011
 @29ns reset 0 enable 1 count 00100
 @31ns reset 0 enable 1 count 00101
 @33ns reset 0 enable 1 count 00110
 @35ns reset 0 enable 1 count 00111
 @37ns reset 0 enable 1 count 01000
 @39ns reset 0 enable 1 count 01001
 @41ns reset 0 enable 1 count 01010

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Deepak Kumar Tala - All rights reserved

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