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  ../images/main/bullet_star_pink.gif Transition bins creation : Set of transition

Like in the case of normal array of bin creation, Systemverilog provides syntax to declare array of transitions. This is called set of transition

   

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  ../images/main/4blue_dots_bullets.gif Example : set bins creation
   

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  1 module test();
  2 
  3 logic [2:0] addr;
  4 reg ce;
  5 
  6 covergroup address_cov () @ (posedge ce);
  7   ADDRESS : coverpoint addr {
  8     // simple transition bin
  9     bins adr_low[]          = (0,1=>2,3);
 10     bins adr_med[]          = (1,2=>3,4);
 11     bins adr_high[]         = (3,4=>5,6);
 12   }
 13 endgroup
 14 
 15 address_cov my_cov = new();
 16 
 17 initial begin
 18   ce   <= 0;
 19   addr <= 0;
 20   $monitor("ce %b addr 8'h%x",ce,addr);
 21   repeat (10) begin
 22     ce <= 1;
 23     addr <= $random;
 24      #10 ;
 25     ce <= 0;
 26      #10 ;
 27   end
 28 end
 29 
 30 endmodule
You could download file set_bin.sv here
   

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  ../images/main/4blue_dots_bullets.gif Simulation : set bins creation
   

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 ce 1 addr 8'h4
 ce 0 addr 8'h4
 ce 1 addr 8'h1
 ce 0 addr 8'h1
 ce 1 addr 8'h1
 ce 0 addr 8'h1
 ce 1 addr 8'h3
 ce 0 addr 8'h3
 ce 1 addr 8'h5
 ce 0 addr 8'h5
 ce 1 addr 8'h5
 ce 0 addr 8'h5
 ce 1 addr 8'h5
 ce 0 addr 8'h5
 ce 1 addr 8'h2
 ce 0 addr 8'h2
 ce 1 addr 8'h1
 ce 0 addr 8'h1
 ce 1 addr 8'h5
 ce 0 addr 8'h5
   

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  ../images/main/4blue_dots_bullets.gif Report : set bins creation
   

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 ===========================================================
 Group : test::address_cov
 ===========================================================
 SCORE  WEIGHT GOAL   
  25.00 1      100    
 -----------------------------------------------------------
 Summary for Group   test::address_cov
 
 CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
 Variables 12       9         3       25.00   
 
 Variables for Group  test::address_cov
 
 VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT 
 ADDRESS  12       9         3       25.00   100  1      
 -----------------------------------------------------------
 Summary for Variable ADDRESS
 
 CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
 User Defined Bins 12       9         3       25.00   
 
 User Defined Bins for ADDRESS
 
 Uncovered bins
 
 NAME          COUNT AT LEAST NUMBER 
 adr_high:3->6 0     1        1      
 adr_high:4->5 0     1        1      
 adr_high:4->6 0     1        1      
 adr_med:1->4  0     1        1      
 adr_med:2->3  0     1        1      
 adr_med:2->4  0     1        1      
 adr_low:0->2  0     1        1      
 adr_low:0->3  0     1        1      
 adr_low:1->2  0     1        1      
 
 Covered bins
 
 NAME          COUNT AT LEAST  
 adr_high:3->5 1     1        
 adr_med:1->3  1     1        
 adr_low:1->3  1     1        
   

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Deepak Kumar Tala - All rights reserved

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