SystemVerilog's OOP implementation provides the capability of inheriting from a base class and extending its capabilities within a subclass. This concept is called inheritance. When one inherits from a class into another, the original class definition is not changed, however the new subclass contains all the properties and methods of the base class and then can optionally add additional properties and methods. SystemVerilog allows inheriting from single parent class. In Vera inheriting from multiple parents is allows as well in C++.

Overridden Members

To override a method means that given a base class with a method, we can define a subclass which extends from that base class and then provide a new definition for the given method. By default, the subclass inherits the base class implementation of the method but should the programmer decide to change that definition by overriding it - simply listing a new version of that method, then the new version of the method will be used instead of the parent's.

Sub Class

To do a full (deep) copy, where everything (including nested objects) is copied, custom code is typically needed.

  1 program class_inherit;
  2 
  3   class A ;
  4     integer j = 5;
  5     task print();
  6       begin
  7         $display("j is %0d",j);
  8       end
  9     endtask
 10   endclass
 11 
 12   class B extends A;
 13     integer i = 1;
 14     // Override the parent class print
 15     task print();
 16       begin
 17         $display("i is %0d",i);
 18         $display("j is %0d",j);
 19       end
 20     endtask
 21   endclass
 22   
 23   initial begin
 24     B b1;
 25     b1 = new;
 26     b1.print();
 27   end
 28 
 29 endprogram

 i is 1
 j is 5

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