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Out-of-block declarations
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Like in C++, and Vera, Class prototype can be declared in header file (*.h in C++ and vri in Vera) for SystemVerilog also. And the body of the functions/tasks can be delcared in seprate file. |
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To do this, add extern to function and task in class header file as in the example below. |
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Code : Out-of-block declarations
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Header File |
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1 `ifndef CLASS_EXTERN_SVI
2 `define CLASS_EXTERN_SVI
3
4 class class_extern;
5 int address;
6 bit [63:0] data;
7 shortint crc;
8
9 extern function new();
10 extern task print();
11 endclass
12
13
14 `endif
You could download file class_extern.svi here
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Body File |
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1 `ifndef CLASS_EXTERN_SV
2 `define CLASS_EXTERN_SV
3
4 `include "class_extern.svi"
5
6 function class_extern::new();
7 this.address = $random;
8 this.data = {$random,$random};
9 this.crc = $random;
10 endfunction
11
12 task class_extern::print();
13 $display("Address : %x",address);
14 $display("Data : %x",data);
15 $display("CRC : %x",crc);
16 endtask
17
18 `endif
You could download file class_extern.sv here
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Program File |
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1 program class_exterm_prg;
2
3 `include "class_extern.sv"
4
5 class_extern c;
6
7 initial begin
8 c = new();
9 c.print();
10 $finish;
11 end
12
13 endprogram
You could download file class_extern_prg.sv here
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Simulation : Out-of-block declarations
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Address : 12153524
Data : c0895e818484d609
CRC : 5663
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Copyright © 1998-2025 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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