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  ../images/main/bullet_star_pink.gif System tasks

To help writing assertions, SystemVerilog provides with system tasks as in list below.

   

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  • $sampled
  • $rose
  • $fell
  • $stable
  • $past
   

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  ../images/main/4blue_dots_bullets.gif $sampled, $rose, $fell, $stable and $past

Function $sampled returned the sampled value of a expression with respect to last clock event. When $sampled is invoked prior to the occurrence of the first clocking event, the value of X is returned. The use of $sampled in assertions, although allowed, is redundant, as the result of the function is identical to the sampled value of the expression itself used in the assertion. But following types are usefull

   

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  • $rose returns true, when least significant bit changes to 1.
  • $fell returns true, when least significant bit changes to 0.
  • $stable returns true, if value did not change since last clock event to current clock event.
  • $past returns value n clock events before.
   

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  ../images/main/4blue_dots_bullets.gif Example : System Tasks
   

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  1 module system_assertion();
  2 
  3 logic clk = 0;
  4 always  #1  clk ++;
  5 
  6 logic req,gnt;
  7 //-------------------------------------------------
  8 // Property Specification Layer
  9 //-------------------------------------------------
 10 property system_prop;
 11   @ (posedge clk) 
 12       ($rose(req) && $past( ! req,1)) |=> 
 13          ($rose(gnt) && $past( ! gnt,1));
 14 endproperty
 15 //-------------------------------------------------
 16 // Assertion Directive Layer
 17 //-------------------------------------------------
 18 system_assert : assert property (system_prop);
 19 //-------------------------------------------------
 20 // Generate input vectors
 21 //-------------------------------------------------
 22 initial begin
 23   req <= 0;gnt <= 0;
 24   repeat(10) @ (posedge clk);
 25   req <= 1;
 26   @( posedge clk);
 27   gnt <= 1;
 28   req <= 0;
 29   @( posedge clk);
 30   // Make the assertion fail now
 31   req <= 0;gnt <= 0;
 32   repeat(10) @ (posedge clk);
 33   req <= 1;
 34   @( posedge clk);
 35   req <= 0;
 36   gnt <= 0;
 37   // Terminate the sim
 38    #30  $finish;
 39 end
 40 
 41 endmodule
You could download file system_assertion.sv here
   

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  ../images/main/4blue_dots_bullets.gif Simulation : System Tasks
   

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 "system_assertion.sv", 18: 
 system_assertion.system_assert: started at 45s failed at 47s
         Offending '($rose(gnt) && $past((!gnt), 1))'
   

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Deepak Kumar Tala - All rights reserved

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