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Clock Resolution
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For concurrent assertion to work, it needs clock, there are multiple ways a clock can be resolved for a concurrent assertion as in the list below. |
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- Sequence instance with a clock : In this clock is specified in sequence declaration itself.
- Property instance with a clock : In this clock is specified in property declaration itself.
- Contextually inferred clock from a procedural block. : In this procedural block trigger resolve to clock.
- Clocking block : A clocking block can be used for resolving the clock.
- default clock : Default clock is another way of clocking block, so same as above.
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Example : Clock Resolution
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1 //+++++++++++++++++++++++++++++++++++++++++++++++++
2 // DUT With assertions
3 //+++++++++++++++++++++++++++++++++++++++++++++++++
4 module clock_resolve_assertion();
5 logic clk = 0;
6 logic req,gnt;
7 //=================================================
8 // Clock inside a sequence
9 //=================================================
10 sequence req_gnt_seq;
11 @ (posedge clk)
12 req ##1 gnt;
13 endsequence
14 //=================================================
15 // Clock inside a property
16 //=================================================
17 property req_gnt_prop;
18 @ (posedge clk)
19 req |=> gnt;
20 endproperty
21 //=================================================
22 // Clock infered from a always block
23 //=================================================
24 always @ (posedge clk)
25 begin
26 gnt <= req;
27 //==============================================
28 // Here clock is infered to be posedge clk
29 //==============================================
30 req_gnt_assert : assert property (req |=> gnt);
31 end
32 //=================================================
33 // Default clocking
34 //=================================================
35 default clocking aclk @ (posedge clk);
36 input req;
37 input gnt;
38 endclocking
39
40 property req_gnt_default_prop;
41 req |-> ##1 gnt;
42 endproperty
43 //=================================================
44 // clocking clocking
45 //=================================================
46 clocking reqclk @ (posedge clk);
47 input req;
48 input gnt;
49 endclocking
50
51 property req_gnt_clocking_prop;
52 reqclk.req |-> ##1 reqclk.gnt;
53 endproperty
54 //+++++++++++++++++++++++++++++++++++++++++++++++++
55 // Now call all the assertion in one go
56 //+++++++++++++++++++++++++++++++++++++++++++++++++
57 a1 : assert property (req_gnt_prop);
58 a2 : assert property (req_gnt_default_prop);
59 a3 : assert property (req_gnt_clocking_prop);
60 //+++++++++++++++++++++++++++++++++++++++++++++++++
61 // Assertion testing code
62 //+++++++++++++++++++++++++++++++++++++++++++++++++
63 always #1 clk ++;
64
65 initial begin
66 $monitor("Req %b Gnt %b",req,gnt);
67 req <= 0; gnt <= 0;
68 // Make the assertion pass
69 ##1 req <= 1;
70 ##20 ;
71 req <= 0;
72 #10 $finish;
73 end
74
75 endmodule
You could download file clock_resolve_assertion.sv here
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Simulation : Clock Resolution
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Req 0 Gnt 0
Req 1 Gnt 0
Req 1 Gnt 1
Req 0 Gnt 1
Req 0 Gnt 0
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
Do you have any Comment? mail me at:deepak@asic-world.com
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