SC_CTHREAD processes typically have infinite loops that will continuously execute. A designer typically wants some way to initialize the behavior of the loop or jump out of the loop when a condition occurs. This is accomplished through the use of the watching construct. The watching construct will monitor a specified condition. When this condition occurs control is transferred from the current execution point to the beginning of the process, where the occurrence of the watched condition can be handled. The watching construct is only available for SC_CTHREAD processes.

The delayed() function is required for the signal in a watching expression in order for the description to compile properly. The delayed() function allows the compiler to identify signals that are used in watching expressions.

One unexpected consequence of control exiting the while loop and starting again at the beginning of the process is that all of the variables defined locally within the process will lose their value. If a variable value is needed to be kept between invocations of the process, declare the variable in the process module, and not local to the process.

In the constructor of the example is the following statement: watching(reset.delayed() == true); This statement specifies that signal reset will be watched for this process. If signal reset changes to true then the watching expression will be true and the SystemC scheduler will halt execution of the while loop for this process and start the execution at the first line of the process.

  1 //-----------------------------------------------------
  2 // This is my second Systemc Example
  3 // Design Name : first_counter
  4 // File Name : first_counter.cpp
  5 // Function : This is a 4 bit up-counter with
  6 // Synchronous active high reset and
  7 // with active high enable signal
  8 //-----------------------------------------------------
  9 #include "systemc.h"
 10 
 11 SC_MODULE (first_counter) {
 12   sc_in_clk     clock ;      // Clock input of the design
 13   sc_in<bool>   reset ;      // active high, synchronous Reset input
 14   sc_in<bool>   enable;      // Active high enable signal for counter
 15   sc_out<sc_uint<4> > counter_out; // 4 bit vector output of the counter
 16 
 17   //------------Local Variables Here---------------------
 18   sc_uint<4>	count;
 19 
 20   //------------Code Starts Here-------------------------
 21   // Below function implements actual counter logic
 22   void incr_count () {
 23     if (reset.read() == 1) {
 24       count =  0;
 25       counter_out.write(count);
 26       cout<<"@" << sc_time_stamp() <<
 27         " :: Watching reset is activated "<<endl;
 28     }
 29     while (true) { 
 30       wait();
 31       // If enable is active, then we increment the counter
 32       if (enable.read() == 1) {
 33         count = count + 1;
 34         counter_out.write(count);
 35       }
 36     }
 37   } // End of function incr_count
 38 
 39   // Below functions prints value of count when ever it changes
 40   void print_count () {
 41     while (true) {
 42       wait();
 43       cout<<"@" << sc_time_stamp() <<
 44         " :: Counter Value "<<counter_out.read()<<endl;
 45     }
 46   }
 47 
 48   // Constructor for the counter
 49   // Since this counter is a positive edge trigged one,
 50   // We trigger the below block with respect to positive
 51   // edge of the clock
 52   SC_CTOR(first_counter) {
 53     // cthreads require to have thread name and triggering 
 54     // event to passed as clock object
 55     SC_CTHREAD(incr_count, clock.pos());
 56       watching(reset.delayed() == true);
 57     // Level Sensitive to change in counter output
 58     SC_THREAD(print_count);
 59       sensitive << counter_out;
 60   } // End of Constructor
 61 
 62 }; // End of Module counter

              SystemC 2.0.1 --- Oct  6 2006 19:17:37
         Copyright (c) 1996-2002 by all Contributors
                     ALL RIGHTS RESERVED
 @0 s Asserting reset
 
 WARNING: Default time step is used for VCD tracing.
 @10 ns De-Asserting reset
 
 @11 ns :: Watching reset is activated
 @13 ns :: Watching reset is activated
 @15 ns :: Watching reset is activated
 @17 ns :: Watching reset is activated
 @19 ns :: Watching reset is activated
 @21 ns :: Watching reset is activated
 @23 ns :: Watching reset is activated
 @25 ns :: Watching reset is activated
 @27 ns :: Watching reset is activated
 @29 ns :: Watching reset is activated
 @40 ns Asserting Enable
 
 @41 ns :: Counter Value 1
 @43 ns :: Counter Value 2
 @45 ns :: Counter Value 3
 @47 ns :: Counter Value 4
 @49 ns :: Counter Value 5
 @51 ns :: Counter Value 6
 @53 ns :: Counter Value 7
 @55 ns :: Counter Value 8
 @57 ns :: Counter Value 9
 @59 ns :: Counter Value 10
 @61 ns :: Counter Value 11
 @63 ns :: Counter Value 12
 @65 ns :: Counter Value 13
 @67 ns :: Counter Value 14
 @69 ns :: Counter Value 15
 @71 ns :: Counter Value 0
 @73 ns :: Counter Value 1
 @75 ns :: Counter Value 2
 @77 ns :: Counter Value 3
 @79 ns :: Counter Value 4
 @80 ns De-Asserting Enable
 
 @80 ns Terminating simulation

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Deepak Kumar Tala - All rights reserved

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