For writing makefile for the simulation is nothing different from writing make file for compiling C or C++ files. One big advantage of the Verilog compilers over the gcc is that, Verilog compilers like VCS and NCverilog seem to keep track of if the file really was modified or not, thus does not recompile it and thus saves compile time.

Below is simple example for a Verilog simulation compile Makefile.

SRC_FILE = counter.v counter_tb.v

COM = vcs

COM_OPTS = -Mupdate -debug

com : counter.v counter_tb.v

$(COM) $(COM_OPTS) $(SRC_FILE)

sim : simv

simv

clean :

@rm -rf simv csrc *.vcd

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