quick.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

   

space.gif

   

space.gif

14-October-2010
  • Completed VMM, AOP, System tasks and functional coverage chapters in systemverilog
7-June-2009
  • Completed Specman functional coverage chapter
  • Completed VERA functional coverage chapter
  • Completed writing of few pages in RVM, will close this fast
10-Jan-2008
  • After a long break, started again with website update
  • Started working on VMM, OVM and RVM
22-July-2007
  • Almost completed the VERA tutorial.
  • Started working on SystemVerilog Section
  • Start new section on PSL. Will finish this in less then 2 Months.
13-Dec-2006
  • Added sections on VHDL and VERA after many requests. This sections are still empty, but plan to complete them much faster than any other section.
13-Oct-2006
  • Almost completed the SystemC tutorial.
  • Added lot of examples to Verilog example section.
  • Fixed tons of grammar and spelling mistakes in Verilog, Digital and Tidbits sections.
28-Sep-2006
  • Started working on completing empty sections in systemc and systemverilog after long break.
12-Dec-2005
  • Removed pdf version of all the tutorials as server speed is getting affected and also due bandwidth issues.
11-Sep-2005
  • Completed the Verilog tutorial.
  • Leaving two chapters in Specman tutorial, all other chapters are completed.
  • Added pdf version of all the tutorials.
28-Oct-2004
  • Added new section on scripting, SystemVerilog, SystemC, Specman and Forum for user to post their questions.
  • Added more examples to verilog tutorial, and fixed tons of typo mistakes in verilog tutorial.
01-Feb-2004
  • Moved from www.deeps.org to www.asic-world.com due to bandwidth problem and poor support from my webhosting company. I plan to keep www.deeps.org alive for couple of years.
01-Jan-2004
  • Removed the Embedded section as the guy who was suppose to contribute is not contributing and I am in no mood to write about embedded systems.
  • Completed the Digital section.
  • Completed Verilog PLI Tutorial ( Ofcourse, I need to add some more examples and details of each routine).
  • Thanks for all the people, who pointed the mistakes and made suggestions.
01-June-2003
  • Added the Verilog FAQ sections with questions and Verilog in One day tutorial.
  • Added embedded section with tutorial, books and Links.
20-Jan-2003
  • I could not update my website on time as I am bit busy spending time with my new born daughter Divya and my beloved wife Durga.
  • Fixed the broken links in Digital and Verilog section. Completed Verilog tutorial, but could not complete the PLI and synthesis tutorial. Digital tutorial still lacking behind.
  • Fixed the FIFO code and gray code counter code, basically it was coded and never compiled to see if there are any syntax errors. Thanks to Dan Blake for pointing this Errors.
07-July-2002
  • Updated Digital section with more tutorials, and changed the look and feel same as Verilog section. Tutorial are nearing completion, more details to each section will be added when I get time.
  • Updated Verilog section with more models, Tutorial are nearing completion, more details to each section will be added when I get time.
  • Changed most of the pages to make it Linux and Unix friendly, Verilog section still pending. Images in all the pages were seen messed up in UNIX browser. Please report the pages which are not UNIX friendly.
  • Added new section on VLSI, This section will be more to do with Backend design. As usual I may take lot of time to complete it.
  • Removed the images which can be put as text to reduce download time.
20-Apr-2002
  • Added my resume, of course I am not looking for a change.
  • For last few weeks, my website is having problem as there has been IP address change of the server. This should get fixed in couple of weeks. For time now, please hit refresh couple of times to get to the pages.
19-Mar-2001
  • Removed all the empty section, updated the Verilog section.
21-may-2000
  • Deleted all the pages at www.deeps.org due to compatibility problems with Netscape navigator and Opera Browser. Seems FrontPage of Microsoft does create problems for non Microsoft browsers. Re-uploaded all the pages after fixing this problem.
14-Sep-1999
  • Added new sections to Verilog, and changed the web page look a bit. Added pages to protect the directory listing
10-Feb-1999
  • Moved from www.angelfire.com/de/deeps to www.deeps.org
1998
  • Decided to have a web page on ASIC design, so started web page at www.angelfire.com. Had small tutorial on Verilog, VHDL and bit of tidbits.
1997
  • Registered my first web page at www.tripod.com and www.geocities.com and few more places, I hope it is still there. It was more of personal web page, more to do with Human psychology, Body language, Astrology and poetry...things I am good at other then my VLSI skills.
   

space.gif

   

space.gif

   

space.gif

space2.gif

space2.gif

space2.gif

space2.gif

space2.gif

  

Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com