Below code is 16-bit CRC-CCITT implementation, with following features

• Width = 16 bits
• Truncated polynomial = 0x1021
• Initial value = 0xFFFF
• Input data is NOT reflected
• Output CRC is NOT reflected
• No XOR is performed on the output CRC

  1 -------------------------------------------------------
  2 -- Design Name : parallel_crc_ccitt
  3 -- File Name   : parallel_crc.vhd
  4 -- Function    : CCITT Parallel CRC
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity parallel_crc_ccitt is
 12     port (
 13         clk     :in  std_logic;
 14         reset   :in  std_logic;
 15         enable  :in  std_logic;
 16         init    :in  std_logic;
 17         data_in :in  std_logic_vector (7 downto 0);
 18         crc_out :out std_logic_vector (15 downto 0)
 19     );
 20 end entity;
 21 
 22 architecture rtl of parallel_crc_ccitt is
 23     signal crc_reg  :std_logic_vector (15 downto 0);
 24     signal next_crc :std_logic_vector (15 downto 0);
 25 begin
 26 
 27     crc_out <= crc_reg;
 28     
 29    -- CRC Control logic
 30     process (clk) begin
 31         if (rising_edge(clk)) then
 32             if (reset = '1') then
 33                 crc_reg <= x"FFFF";
 34             elsif (enable = '1') then
 35                 if (init = '1') then
 36                     crc_reg <= x"FFFF";
 37                 else
 38                     crc_reg <= next_crc;
 39                 end if;
 40             end if;
 41         end if;
 42     end process;
 43     
 44    -- Parallel CRC calculation
 45     next_crc(0)  <= data_in(7) xor data_in(0) xor crc_reg(4) 
 46                     xor crc_reg(11);
 47     next_crc(1)  <= data_in(1) xor crc_reg(5);
 48     next_crc(2)  <= data_in(2) xor crc_reg(6);
 49     next_crc(3)  <= data_in(3) xor crc_reg(7);
 50     next_crc(4)  <= data_in(7) xor data_in(5) xor data_in(0) 
 51                     xor crc_reg(4) xor crc_reg(9) xor crc_reg(11);
 52     next_crc(6)  <= data_in(6) xor data_in(1) xor crc_reg(5) 
 53                     xor crc_reg(10);
 54     next_crc(7)  <= data_in(7) xor data_in(2) xor crc_reg(6) 
 55                     xor crc_reg(11);
 56     next_crc(8)  <= data_in(3) xor crc_reg(0) xor crc_reg(7);
 57     next_crc(9)  <= data_in(4) xor crc_reg(1) xor crc_reg(8);
 58     next_crc(10) <= data_in(5) xor crc_reg(2) xor crc_reg(9);
 59     next_crc(11) <= data_in(6) xor crc_reg(3) xor crc_reg(10);
 60 end architecture;

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Deepak Kumar Tala - All rights reserved

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