1 -------------------------------------------------------
  2 -- Design Name : dlatch_reset
  3 -- File Name   : dlatch_reset.vhd
  4 -- Function    : DLATCH async reset
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity dlatch_reset is
 12     port (
 13         data  :in  std_logic;-- Data input
 14         en    :in  std_logic;-- Enable input
 15         reset :in  std_logic;-- Reset input
 16         q     :out std_logic -- Q output
 17 
 18     );
 19 end entity;
 20 
 21 architecture rtl of dlatch_reset is
 22 
 23 begin
 24     process (en, reset, data) begin
 25         if (reset = '0') then
 26             q <= '0';
 27         elsif (en = '1') then
 28             q <= data;
 29         end if;
 30     end process;
 31 
 32 end architecture;

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