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  ../../images/main/bullet_green_ball.gif VHDL Round Robin Arbiter Model
   

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   1 ------------------------------------------------------
   2 -- A four level, round-robin arbiter. This was 
   3 -- orginally coded by WD Peterson in VHDL. 
   4 -- Coder       : Deepak Kumar Tala (Verilog) 
   5 -- Translator  : Alexander H Pham (VHDL) 
   6 ------------------------------------------------------
   7 library ieee;
   8     use ieee.std_logic_1164.all;
   9 
  10 entity arbiter is
  11     port (
  12         clk,  rst  :in  std_logic;
  13         req0, req1 :in  std_logic;
  14         req2, req3 :in  std_logic;
  15         gnt0, gnt1 :out std_logic;
  16         gnt2, gnt3 :out std_logic
  17     );
  18 end entity;
  19 architecture behavior of arbiter is
  20 
  21    ----------------Internal Registers-----------------
  22     signal gnt,    lgnt    :std_logic_vector (1 downto 0);
  23     signal comreq, lcomreq :std_logic;
  24     signal beg,    ledge   :std_logic;
  25     signal lgnt0,  lgnt1   :std_logic;
  26     signal lgnt2,  lgnt3   :std_logic;
  27     signal lmask0, lmask1  :std_logic;
  28     signal lasmask         :std_logic;
  29 
  30 begin
  31 
  32    ----------------Code Starts Here------------------
  33     process (clk) begin
  34         if (rising_edge(clk)) then
  35             if (rst = '1') then
  36                 lgnt0 <= '0';
  37                 lgnt1 <= '0';
  38                 lgnt2 <= '0';
  39                 lgnt3 <= '0';
  40             else
  41                 lgnt0 <=(not lcomreq and not lmask1 and not lmask0 and
  42                          not req3 and not req2 and not req1 and req0)
  43                      or (not lcomreq and not lmask1 and lmask0 and
  44                          not req3 and not req2 and req0)
  45                      or (not lcomreq and lmask1 and not lmask0 and
  46                          not req3 and req0)
  47                      or (not lcomreq and lmask1 and lmask0 and req0)
  48                      or (lcomreq and lgnt0);
  49                      
  50                 lgnt1 <=(not lcomreq and not lmask1 and not lmask0 and req1)
  51                      or (not lcomreq and not lmask1 and lmask0 and
  52                          not req3 and not req2 and req1 and not req0)
  53                      or (not lcomreq and lmask1 and not lmask0 and
  54                          not req3 and req1 and not req0)
  55                      or (not lcomreq and lmask1 and lmask0 and
  56                              req1 and not req0)
  57                      or (lcomreq and lgnt1);
  58                      
  59                 lgnt2 <=(not lcomreq and not lmask1 and not lmask0 and
  60                              req2 and not req1)
  61                      or (not lcomreq and not lmask1 and lmask0 and req2)
  62                      or (not lcomreq and lmask1 and not lmask0 and
  63                          not req3 and req2 and not req1 and not req0)
  64                      or (not lcomreq and lmask1 and lmask0 and
  65                              req2 and not req1 and not req0)
  66                      or (lcomreq and lgnt2);
  67                      
  68                 lgnt3 <=(not lcomreq and not lmask1 and not lmask0 and
  69                              req3 and not req2 and not req1)
  70                      or (not lcomreq and not lmask1 and lmask0 and
  71                              req3 and not req2)
  72                      or (not lcomreq and lmask1 and not lmask0 and req3)
  73                      or (not lcomreq and lmask1 and lmask0 and
  74                              req3 and not req2 and not req1 and not req0)
  75                      or (lcomreq and lgnt3);
  76             end if;
  77         end if;
  78     end process;
  79 
  80    ------------------------------------------------------
  81    -- lasmask state machine.
  82    ------------------------------------------------------
  83     beg <= (req3 or req2 or req1 or req0) and not lcomreq;
  84     process (clk) begin
  85         if (rising_edge(clk)) then
  86             lasmask <= (beg and not ledge and not lasmask);
  87             ledge   <= (beg and not ledge and     lasmask)
  88                    or  (beg and     ledge and not lasmask);
  89         end if;
  90     end process;
  91 
  92    ------------------------------------------------------
  93    -- comreq logic.
  94    ------------------------------------------------------
  95     lcomreq <= (req3 and lgnt3)
  96             or (req2 and lgnt2)
  97             or (req1 and lgnt1)
  98             or (req0 and lgnt0);
  99 
 100    ------------------------------------------------------
 101    -- Encoder logic.
 102    ------------------------------------------------------
 103     lgnt <=  ((lgnt3 or lgnt2) & (lgnt3 or lgnt1));
 104 
 105    ------------------------------------------------------
 106    -- lmask register.
 107    ------------------------------------------------------
 108     process (clk) begin
 109         if (rising_edge(clk)) then
 110             if (rst = '1') then
 111                 lmask1 <= '0';
 112                 lmask0 <= '0';
 113             elsif (lasmask = '1') then
 114                 lmask1 <= lgnt(1);
 115                 lmask0 <= lgnt(0);
 116             else
 117                 lmask1 <= lmask1;
 118                 lmask0 <= lmask0;
 119             end if;
 120         end if;
 121     end process;
 122 
 123     comreq <= lcomreq;
 124     gnt    <= lgnt;
 125    ------------------------------------------------------
 126    -- Drive the outputs
 127    ------------------------------------------------------
 128     gnt3   <= lgnt3;
 129     gnt2   <= lgnt2;
 130     gnt1   <= lgnt1;
 131     gnt0   <= lgnt0;
 132 
 133 end architecture;
 134 
 135 ------------------------------------------------------
 136 -- Arbiter test bench
 137 ------------------------------------------------------
 138 library ieee;
 139     use ieee.std_logic_1164.all;
 140     use ieee.std_logic_unsigned.all;
 141     use ieee.std_logic_textio.all;
 142     use std.textio.all;
 143 
 144 entity arbiter_tb is
 145 end entity;
 146 architecture test of arbiter_tb is
 147     signal clk        :std_logic := '0';
 148     signal rst        :std_logic := '1';
 149     signal req0, req1 :std_logic := '0';
 150     signal req2, req3 :std_logic := '0';
 151     signal gnt0, gnt1 :std_logic := '0';
 152     signal gnt2, gnt3 :std_logic := '0';
 153     
 154     component arbiter is
 155     port (
 156         clk,  rst  :in  std_logic;
 157         req0, req1 :in  std_logic;
 158         req2, req3 :in  std_logic;
 159         gnt0, gnt1 :out std_logic;
 160         gnt2, gnt3 :out std_logic
 161     );
 162     end component;
 163     
 164     constant PERIOD :time := 20 ns;
 165 
 166 begin
 167    -- Clock generator
 168     clk <= not clk after PERIOD/2;
 169     rst <= '0'     after PERIOD;
 170     
 171     req0 <= '1' after PERIOD*1, '0' after PERIOD*2,
 172             '1' after PERIOD*3, '0' after PERIOD*7;
 173 
 174     req1 <= '1' after PERIOD*3, '0' after PERIOD*4;
 175 
 176     req2 <= '1' after PERIOD*4, '0' after PERIOD*5;
 177 
 178     req3 <= '1' after PERIOD*5, '0' after PERIOD*6;
 179 
 180    -- Connect the DUT
 181     Inst_arbiter : arbiter
 182     port map(
 183         clk  => clk,
 184         rst  => rst,
 185         req0 => req0,
 186         req1 => req1,
 187         req2 => req2,
 188         req3 => req3,
 189         gnt0 => gnt0,
 190         gnt1 => gnt1,
 191         gnt2 => gnt2,
 192         gnt3 => gnt3
 193     );
 194 
 195 end architecture;
You could download file vhdl_examples here
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com