1 #ifndef MEM_IF_VRH
  2 #define MEM_IF_VRH
  3 
  4 #include "vera_defines.vrh"
  5 
  6 interface mem_if {
  7   input        clock      CLOCK;
  8   inout        chip_en    PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1 ;
  9   inout        read_write PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1 ;
 10   inout [7:0]  address    PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1 ;
 11   inout [7:0]  data_in    PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1 ;
 12   inout [7:0]  data_out   PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1 ;
 13 }
 14 
 15 #endif

  1 #ifndef MEM_PORTS_VRH
  2 #define MEM_PORTS_VRH
  3 
  4 port mem_ports {
  5  clock;
  6  address;
  7  chip_en;
  8  read_write;
  9  data_in;
 10  data_out;
 11 }
 12 
 13 #endif

  1 #ifndef MEM_BINDS_VRH
  2 #define MEM_BINDS_VRH
  3 
  4 bind mem_ports mem_p {
  5  clock        mem_if.clock     ;
  6  address      mem_if.address   ;
  7  chip_en      mem_if.chip_en   ;
  8  read_write   mem_if.read_write;
  9  data_in      mem_if.data_in   ;
 10  data_out     mem_if.data_out  ;
 11 }
 12 
 13 #endif

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