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FIFO Scoreboard
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1 class fifo_sb {
2 integer fifo;
3 integer size;
4
5 task new() {
6 size = 0;
7 fifo = alloc(MAILBOX,0,1);
8 }
9
10 task addItem(bit [7:0] data) {
11 if (size == 7) {
12 printf("%dns : ERROR : Over flow detected, current occupancy %d\n",
13 get_cycle(), size);
14 } else {
15 mailbox_put (fifo,data);
16 size ++;
17 }
18 }
19
20 task compareItem (bit [7:0] data) {
21 bit [7:0] cdata = 0;
22 if (size == 0) {
23 printf("%dns : ERROR : Under flow detected\n", get_cycle());
24 } else {
25 mailbox_get (WAIT,fifo, cdata);
26 if (data ! = cdata) {
27 printf("%dns : ERROR : Data mismatch, Expected %x Got %x\n",
28 get_cycle(), cdata, data );
29 }
30 size --;
31 }
32 }
33 }
You could download file vera_examples here
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FIFO Driver
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1 class fifo_driver {
2 fifo_sb sb;
3 fifo_ports ports;
4
5 bit rdDone;
6 bit wrDone;
7
8 integer wr_cmds;
9 integer rd_cmds;
10
11 task new () {
12 ports = fifo_p;
13 sb = new();
14 wr_cmds = 5;
15 rd_cmds = 5;
16 rdDone = 0;
17 wrDone = 0;
18 ports.$wr_cs = 0;
19 ports.$rd_cs = 0;
20 ports.$wr_en = 0;
21 ports.$rd_en = 0;
22 ports.$data_in = 0;
23 }
24
25 task monitorPush() {
26 bit [7:0] data = 0;
27 while (1) {
28 @ (posedge ports.$clk);
29 if (ports.$wr_cs== 1 && ports.$wr_en== 1) {
30 data = ports.$data_in;
31 sb.addItem(data);
32 printf("%dns : Write posting to scoreboard data = %x\n",get_cycle(), data);
33 }
34 }
35 }
36
37 task monitorPop() {
38 bit [7:0] data = 0;
39 while (1) {
40 @ (negedge ports.$clk);
41 if (ports.$rd_cs== 1 && ports.$rd_en== 1) {
42 data = ports.$data_out;
43 sb.compareItem(data);
44 printf("%dns : Read posting to scoreboard data = %x\n",get_cycle(), data);
45 }
46 }
47 }
48
49 task go() {
50 // Assert reset first
51 reset();
52 // Start the monitors
53 repeat (5) @ (posedge ports.$clk);
54 printf("%dns : Starting Pop and Push monitors\n",get_cycle());
55 fork
56 { monitorPop(); }
57 { monitorPush(); }
58 join none
59 printf("%dns : Starting Pop and Push generators\n",get_cycle());
60 fork
61 { genPush(); }
62 { genPop(); }
63 join none
64
65 while ( ! rdDone && ! wrDone) {
66 @ (posedge ports.$clk);
67 }
68 repeat (10) @ (posedge ports.$clk);
69 printf("%dns : Terminating simulations\n",get_cycle());
70 }
71
72 task reset() {
73 repeat (5) @ (posedge ports.$clk);
74 printf("%dns : Asserting reset\n",get_cycle());
75 ports.$rst= 1'b1;
76 // Init all variables
77 rdDone = 0;
78 wrDone = 0;
79 repeat (5) @ (posedge ports.$clk);
80 ports.$rst= 1'b0;
81 printf("%dns : Done asserting reset\n",get_cycle());
82 }
83
84 task genPush() {
85 bit [7:0] data = 0;
86 integer i = 0;
87 for ( i = 0; i < wr_cmds; i++) {
88 data = random();
89 @ (posedge ports.$clk);
90 while (ports.$full== 1'b1) {
91 ports.$wr_cs = 1'b0;
92 ports.$wr_en = 1'b0;
93 ports.$data_in= 8'b0;
94 @ (posedge ports.$clk);
95 }
96 ports.$wr_cs = 1'b1;
97 ports.$wr_en = 1'b1;
98 ports.$data_in= data;
99 }
100 @ (posedge ports.$clk);
101 ports.$wr_cs = 1'b0;
102 ports.$wr_en = 1'b0;
103 ports.$data_in= 8'b0;
104 repeat (10) @ (posedge ports.$clk);
105 wrDone = 1;
106 }
107
108 task genPop() {
109 integer i = 0;
110 for ( i = 0; i < rd_cmds; i++) {
111 @ (posedge ports.$clk);
112 while (ports.$empty== 1'b1) {
113 ports.$rd_cs = 1'b0;
114 ports.$rd_en = 1'b0;
115 @ (posedge ports.$clk);
116 }
117 ports.$rd_cs = 1'b1;
118 ports.$rd_en = 1'b1;
119 }
120 @ (posedge ports.$clk);
121 ports.$rd_cs = 1'b0;
122 ports.$rd_en = 1'b0;
123 repeat (10) @ (posedge ports.$clk);
124 rdDone = 1;
125 }
126 }
You could download file vera_examples here
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Interface File
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1
2 #define DATA_WIDTH 8
3
4 interface fifo_if {
5 input clk CLOCK;
6 inout rst PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1;
7 inout wr_cs PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1;
8 inout rd_cs PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1;
9 inout rd_en PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1;
10 inout wr_en PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1;
11 inout [DATA_WIDTH-1:0] data_in PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1;
12 inout full PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1;
13 inout empty PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1;
14 inout [DATA_WIDTH-1:0] data_out PHOLD NHOLD #1 PSAMPLE NSAMPLE #-1;
15 }
You could download file vera_examples here
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Ports File
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1
2 port fifo_ports {
3 clk ;
4 rst ;
5 wr_cs ;
6 rd_cs ;
7 rd_en ;
8 wr_en ;
9 data_in ;
10 full ;
11 empty ;
12 data_out ;
13 }
You could download file vera_examples here
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Binds File
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1
2 bind fifo_ports fifo_p {
3 clk fifo_if.clk ;
4 rst fifo_if.rst ;
5 wr_cs fifo_if.wr_cs ;
6 rd_cs fifo_if.rd_cs ;
7 rd_en fifo_if.rd_en ;
8 wr_en fifo_if.wr_en ;
9 data_in fifo_if.data_in ;
10 full fifo_if.full ;
11 empty fifo_if.empty ;
12 data_out fifo_if.data_out;
13 }
You could download file vera_examples here
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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