This section is about general questions asked on Verilog.

Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 15000 active designers.

I have seen many people asking this question; well, the simple answer would be Verilog is similar to C and VHDL is similar to ADA. Verilog is simple to learn and simple to write code in. VHDL on the other hand takes longer time to learn and is bit complicated for writing code. Of course this applies to the engineers who are new to these two languages.

Verilog HDL originated circa 1983 at Gateway Design Automation, which was then located in Acton, MA. The company was privately held at that time by Dr. Prabhakar Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems.

Moorby built a simulator around Verilog-XL in 1984-85, and then went on to make his second major contribution at GDA, viz. the XL algorithm for every fast gate-level simulation, which was first productized in 1986.

Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989. Up to that time, Verilog HDL had still been a proprietary language, being the property of Cadence Design Systems.

Cadence Design Systems decided to open the language to the public in 1990, and thus OVI was born.

When OVI was formed in 1991, a number of small companies began working on Verilog simulators. The first of these came to market in 1992, and now there are mature Verilog simulators available from several sources.

As a result, the Verilog market has grown substantially. The market for Verilog-related tools in 1994 was well over $75m, making it the most commercially significant hardware description language on the market.

Verilog has now been standardized by the IEEE. There is an IEEE working group established under the Design Automation Sub-Committee which was established in 1993 to produce the IEEE Verilog standard 1364. This working group has come out with the Verilog 2001 standard.

Now IEEE is again working on adding new features to Verilog 2001 standard. This new features are called SystemVerilog.

comp.lang.verilog is an unmoderated newsgroup which passed its vote for creation by 332:9 as reported in news.announce.newgroups on 12 Dec 1991.

For your newsgroups file:

comp.lang.verilog Discussing Verilog and PLI.

The charter, culled from the call for votes:

The USENET group is intended at providing a forum for the discussion of topics specific to Verilog, PLI (programming language interface), SDF (Standard delay file format), Synthesis guidelines, compliance and Verilog modeling. It will also provide users with an ability to share Verilog/PLI utilities. Users can also use the forum to discuss any Verilog related issues proposed by Open Verilog International and its organizational and technical committees.

Yes. Users can access this newsgroup through www.google.com news group page. This server provides lots of useful features for searching and viewing the messages posted in any newsgroup and not just comp.lang.verilog. These days no one posts Verilog FAQ in this newsgroup.

Yes, it's available in the web at the following URLs, but most of them are very old; still you may find it useful.

http://www.faqs.org/faqs/verilog-faq/</a> : This site has 1995 version of FAQ

http://www.siliconlogic.com/Verilog/comp.lang.verilog/</a> : Same 1995 version

PLI stands for Programming Language Interface. The PLI consists of an interface mechanism, a set of routines to interact with the simulation environment, and a set of routines to access the Verilog internal data structures. These allow user supplied C code to interact dynamically with the simulation and data structures. Refer to PLI tutorial section

• Verilog PLI Tutorial : This tutorial covers both PLI 1.0 and VPI with good examples.
• Verilog PLI using Java : The Open Verification Environment for the Java (TM) Platform. Jove is a set of Java APIs and tools to enable Verilog hardware design verification of ASICs and FPGAs using the Java programming language.
• Hot PLI Stuff : You can find few examples on writing PLI applications like fileio.
• Project VeriPage : Your one stop source for Verilog Programming Language Interface (PLI) resources

Yes. There are some Verilog parsers available on web:

• verilog 1995 Verilog-Parser-0.13 : This is written in Perl. I have not tried it yet. Maybe when I find time I will try and give a feedback on it.
• The Rough Verilog Parser : This is a rough Verilog parser written in perl , to be used with Verilog to HTML converter. Now supports Verilog 2001.

Refer to tools sections for details on this.

• Commit : Comit Quick Reference Cards for Verilog
• Qualis : Qualis Design. Verilog quick reference card (37-pages!)
• On-line Verilog quick reference guide : The best one.
• Verilog Quick Reference
• Verilog Quick reference Card
• Quick reference for Verilog

Here are some links to Verilog related sites:

• www.cadmazing.com : Cadmazing's DA-Related Information on the Web.
• www.eetimes.com: EEtimes website for daily news on EDA and ASIC.

There are many ways to learn Verilog: you can go through tutorial written by me, else buy some good books in the Books section. Once you have completed reading, you could download the student version of a simulator available in the web. Try designing an I8155 (while teaching Verilog, I have found that 8155 is a very good chip for students to master Verilog).

Once coding and simulation is done, try to get some student version of synthesis tools to see if you can synthesize the code.

There are tons of technical papers available on net, some good papers are ...

• "full_case parallel_case", the Evil Twins of Verilog Synthesis
• Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!
• Correct Methods For Adding Delays to Verilog Behavioral Models

For more papers you could visit http://www.sunburst-design.com/papers/

There are very few of them, you could find one at

• http://www.parmita.com/verilogcenter/quest.html
• Verilog Interview questions

Not yet; I tried to find it on the net and I don't see any such thing. The best thing that you could do is to attend some good interviews !!!

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Deepak Kumar Tala - All rights reserved

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