signal_connect function assigns interface signals to por signals at runtime. It has two uses.

• Static connection: Connect port signals to existing port signals and existing interface signals.
• Dynamic connection: Connect port signals to dynamically created interface signals

Syntax

function integer signal_connect(signal port_signal, string|signal
target_signal [,attributes ][, string|signal clock]);

Where:

• port_signal : Is the signal being mapped. It must be a member of an instantiated port variable.
• target_signal : Is the signal to which the port_signal is connected. It can be an interface signal or a port variable.
• attributes : Is a string that specifies how the new connection is made. Within the string, multiple attributes can be assigned in any order. The string is case-insensitive. Table below shows all the attributes.
• clock : Specifies the clock to which the port_signal is synchronized. It must be a 1-bit signal (subfields are not allowed).

Note:signal_connect() returns a 1 if successful and a 0 if not. Errors in signal_connect() are fatal if the target_signal or clock_signal does not exist, or does not have PLI access permissions, the error is fatal.

There are two types of signal connect, dynamic and static. Dynamic has great impact of performance. Below example is static signal_connect example.

  1 #include "vera_defines.vrh"
  2 
  3 
  4 // This is what connects with HDL
  5 interface count_if {
  6  input clock      CLOCK;
  7  output reset     PHOLD#1;
  8  output enable    PHOLD#1;
  9  input [7:0] cout PSAMPLE #-1;
 10 }
 11 
 12 // Port Declaration
 13 port count_p {
 14   clock;
 15   reset;
 16   enable;
 17   cout;
 18 }
 19 // Top level program 
 20 program signal_connect_ex {
 21    count_p count = new;
 22    signal_connect(count.$clock, count_if.clock);
 23    signal_connect(count.$reset, count_if.reset);
 24    signal_connect(count.$enable,count_if.enable);
 25    signal_connect(count.$cout,  count_if.cout);
 26    // Start the actual test here
 27    @ (posedge count.$clock);
 28    printf("Asserting Reset\n");
 29    count.$reset = 1;
 30    count.$enable = 0;
 31    @ (posedge count.$clock);
 32    printf("Deasserting Reset\n");
 33    count.$reset = 0;
 34    @ (posedge count.$clock);
 35    printf("Asserting Enable\n");
 36    count.$enable = 1;
 37    repeat(10) {
 38      @ (posedge count.$clock);
 39      printf("Counter value %x\n",count.$cout);
 40    }
 41    @ (posedge count.$clock);
 42    printf("Deasserting Enable\n");
 43    count.$enable = 0;
 44 }

Verilog

  1 module top ();
  2 // Internal variables
  3 reg [3:0] counter;
  4 reg       clk;
  5 wire      rst;
  6 wire      enable;
  7 // Connect the program here
  8 signal_connect_ex vshell(
  9  .SystemClock (clk),
 10  .\count_if.clock       (clk),
 11  .\count_if.reset       (rst),
 12  .\count_if.enable      (enable),
 13  .\count_if.cout        (counter)
 14 );
 15 // Init all the variables
 16 initial begin
 17   clk = 0;
 18 end
 19 // Clock generator
 20 always  #1  clk = ~clk;
 21 // Counter code
 22 always @ (posedge clk)
 23   if (rst) counter <= 0;
 24   else if (enable) counter <= counter + 1;
 25 
 26 endmodule

 Asserting Reset
 Deasserting Reset
 Asserting Enable
 Counter value 00
 Counter value 01
 Counter value 02
 Counter value 03
 Counter value 04
 Counter value 05
 Counter value 06
 Counter value 07
 Counter value 08
 Counter value 09
 Deasserting Enable

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Deepak Kumar Tala - All rights reserved

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