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  ../images/main/bulllet_4dots_orange.gif dont_initialize()

Process and threads (not the cthreads) get executed automatically in Constrcutor even if event in sensitivity list does not occur. To prevent this unintensional execution, use dont_initialize() function as shown in example.

   

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  ../images/main/bullet_star_pink.gif Example : dont_initialize()
   

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  1 #include "systemc.h"
  2 
  3 SC_MODULE (tff_sync_reset) {
  4   sc_in    <bool> data, clk, reset  ;
  5   sc_out   <bool> q;
  6 
  7   bool q_l ;
  8 
  9   void tff () {
 10     if (reset.read()) {
 11       q_l = 0;
 12     } else if (data.read()) {
 13       q_l =  ! q_l;
 14     }
 15     q.write(q_l);
 16   }
 17 
 18   SC_CTOR(tff_sync_reset) {
 19     SC_METHOD (tff);
 20       dont_initialize();
 21       sensitive << clk.pos();
 22   }
 23 
 24 };
 25 
 26 SC_MODULE (tff_tb) {
 27   sc_in<bool> clk;
 28  
 29   sc_signal <bool> data, reset  ;
 30   sc_signal   <bool> q;
 31   tff_sync_reset *dut;
 32 
 33   void do_test() {
 34     cout << "@" << sc_time_stamp() <<" Starting test"<<endl;
 35     wait();
 36     cout << "@" << sc_time_stamp() <<" Asserting reset"<<endl;
 37     reset = true; 
 38     wait(4);
 39     cout << "@" << sc_time_stamp() <<" De-Asserting reset"<<endl;
 40     reset = false; 
 41     wait(3);
 42     cout << "@" << sc_time_stamp() <<" Asserting Data input"<<endl;
 43     data = true; 
 44     wait(3);
 45     data = false; 
 46     cout << "@" << sc_time_stamp() <<" De-Asserting Data input"<<endl;
 47     wait(3);
 48     cout << "@" << sc_time_stamp() <<" Terminating simulation"<<endl;
 49     sc_stop();
 50   }
 51 
 52   SC_CTOR(tff_tb) {
 53     dut = new tff_sync_reset ("TFF");
 54     dut->clk    (clk);
 55     dut->reset  (reset);
 56     dut->data   (data);
 57     dut->q      (q);
 58     SC_THREAD (do_test);
 59       dont_initialize();
 60       sensitive << clk.pos();
 61   }
 62 };
 63 
 64 int sc_main (int argc, char* argv[]) {
 65   sc_clock clock ("my_clock",1,0.5);
 66 
 67   tff_tb  object("TFF_TB");
 68     object.clk (clock.signal());
 69   sc_trace_file *wf = sc_create_vcd_trace_file("tff");
 70     sc_trace(wf, object.clk, "clk");
 71     sc_trace(wf, object.reset, "reset");
 72     sc_trace(wf, object.data, "data");
 73     sc_trace(wf, object.q, "q");
 74 
 75   sc_start(0);
 76   sc_start();
 77   sc_close_vcd_trace_file(wf);
 78   return 0;// Terminate simulation
 79 }
You could download file dont_initialize.cpp here
   

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  ../images/main/bullet_star_pink.gif Simulation Output : dont_initialize()
   

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 @0 s Starting test
 WARNING: Default time step is used for VCD tracing.
 @1 ns Asserting reset
 @5 ns De-Asserting reset
 @8 ns Asserting Data input
 @11 ns De-Asserting Data input
 @14 ns Terminating simulation
 SystemC: simulation stopped by user.
   

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  ../images/main/bulllet_4dots_orange.gif Wait Until

In an SC_CTHREAD process wait_until() methods can be used to control the execution of the process. The wait_until() method will halt the execution of the process until a specific event has occurred. This specific event is specified by the expression to the wait_until() method.

   

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This statement will halt execution of the process until the new value of "expr" is true. The delayed() method is required to get the correct value of the object. A compilation error will result if the delayed() method is not present. Only a boolean expression is allowed as argument of the wait_until() function and only boolean signal objects can be used in the boolean expressions. Boolean signal objects include clock type sc_clock, signal type sc_signal, and port types sc_in, sc_out, and sc_inout

   

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  ../images/main/bullet_star_pink.gif Example : Wait Until
   

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  1 //-----------------------------------------------------
  2 // This is my second Systemc Example
  3 // Design Name : first_counter
  4 // File Name : first_counter.cpp
  5 // Function : This is a 4 bit up-counter with
  6 // Synchronous active high reset and
  7 // with active high enable signal
  8 //-----------------------------------------------------
  9 #include "systemc.h"
 10 
 11 SC_MODULE (first_counter) {
 12   sc_in_clk     clock ;      // Clock input of the design
 13   sc_in<bool>   reset ;      // active high, synchronous Reset input
 14   sc_in<bool>   enable;      // Active high enable signal for counter
 15   sc_out<sc_uint<4> > counter_out; // 4 bit vector output of the counter
 16 
 17   //------------Local Variables Here---------------------
 18   sc_uint<4>	count;
 19 
 20   //------------Code Starts Here-------------------------
 21   // Below function implements actual counter logic
 22   void incr_count () {
 23     // For threads, we need to have while true loop
 24     while (true) { 
 25       // Wait until rest is true or enable is true
 26       // Every wait_until delays execution by one clock.pos()
 27       wait_until(reset.delayed() == true || enable.delayed() == true);
 28       if (reset.read() == 1) {
 29         count =  0;
 30         counter_out.write(count);
 31       // If enable is active, then we increment the counter
 32       } else if (enable.read() == 1) {
 33         count = count + 1;
 34         counter_out.write(count);
 35       }
 36     }
 37   } // End of function incr_count
 38 
 39   // Below functions prints value of count when ever it changes
 40   void print_count () {
 41     while (true) {
 42       wait();
 43       cout<<"@" << sc_time_stamp() <<
 44         " :: Counter Value "<<counter_out.read()<<endl;
 45     }
 46   }
 47 
 48   // Constructor for the counter
 49   // Since this counter is a positive edge trigged one,
 50   // We trigger the below block with respect to positive
 51   // edge of the clock
 52   SC_CTOR(first_counter) {
 53     // Edge sensitive to clock
 54     SC_CTHREAD(incr_count, clock.pos());
 55     // Level Sensitive to change in counter output
 56     SC_THREAD(print_count);
 57     sensitive << counter_out;
 58   } // End of Constructor
 59 
 60 }; // End of Module counter
You could download file counter_wait_until.cpp here
   

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Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

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