Scripting Tools




		Simulators Verilog-XL : This is the most standard simulator in the market, as this is the sign off simulator. NCVerilog : This is the compiled simulator which works as fast as VCS, and still maintains the sign off capabilities of Verilog-XL. This simulator is good when it comes to gate level simulations. VCS : This is worlds fastest simulator, this is also a compiled simulator like NCverilog. This simulator is faster when it comes to RTL simulation. Few more things about this simulator are direct C kernel interface, Covermeter code coverage embedded, better integration with VERA and other Synopsys tools. Finsim : This is 100% compatible simulator with Verilog-XL, runs on Linux, Windows and Solaris. This is compiled simulator like VCS and NCVerilog, but slower then VCS and NCVerilog. A $100 version is available, but I wonder what good this can do to Students ? Modelsim : This is most popular simulator, It has got very good debugger, it supports SystemC, Verilog, VHDL and SystemVerilog. Smash : mixed signal (spice), Verilog, VHDL simulator. Silos : I don't know if anyone is using this, Use to be fast and stable. Veritak : Verilog HDL Compiler/Simulator supporting major Verilog 2001 HDL features. It is integral environment including VHDL to Verilog translator, syntax highlight editor (Veripad), class hierarchy viewer ,multiple waveform viewer ,source analyzer,and more --available for Windows XP/2000. If you are looking for fast verilog HDL simulator with very good GUI for professional use, while keeping extremely inexpensive price , this is it. You can try Veritak for free for two weeks. This simulator costs around $50. MPSim : Axiom's MPSim is an integrated verification environment combining the fastest simulator in the industry with advanced testbench automation, assertion-based verification, debugging, and coverage analysis. Personally I have seen this simulator to be faster then NCsim, it comes with build in Vera support. VeriLogger Pro : This simulator has a very easy to use debugging environment that includes a built-in graphical test bench generator. The top-level module ports can be extracted into a timing diagram window that lets the user quickly draw waveforms to describe input stimulus. The test bench is generated automatically and results are displayed in the timing diagram window.

Do you have any Comment? mail me at:deepak@asic-world.com