1 -------------------------------------------------------
  2 -- Design Name : rom_using_file
  3 -- File Name   : rom_using_file.vhd
  4 -- Function    : ROM using readmemh
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10     use ieee.std_logic_unsigned.all;
 11     use ieee.std_logic_textio.all;
 12     use std.textio.all;
 13 
 14 entity rom_using_file is
 15     port (
 16         ce      :in  std_logic;                    -- Chip Enable
 17         read_en :in  std_logic;                    -- Read Enable
 18         address :in  std_logic_vector (7 downto 0);-- Address input
 19         data    :out std_logic_vector (7 downto 0) -- Data output
 20     );
 21 end entity;
 22 architecture behavior of rom_using_file is
 23 
 24    -- RAM block 8x256
 25     type RAM is array (integer range <>)of std_logic_vector (7 downto 0);
 26     signal mem : RAM (0 to 255);
 27 
 28    -- Subprogram to read a text file into RAM 29     procedure Load_ROM (signal data_word :inout RAM) is
 30        -- Open File in Read Mode
 31         file romfile   :text open read_mode is "memory.list";
 32         variable lbuf  :line;
 33         variable i     :integer := 0;
 34         variable fdata :std_logic_vector (7 downto 0);
 35     begin
 36         while not endfile(romfile) loop
 37            -- read digital data from input file
 38             readline(romfile, lbuf);
 39             read(lbuf, fdata);
 40             data_word(i) <= fdata;
 41             i := i+1;
 42         end loop;
 43     end procedure;
 44 
 45 begin
 46 
 47    -- Procedural Call 48     Load_ROM(mem);
 49 
 50     data <= mem(conv_integer(address)) when (read_en = '1' and ce = '1') else (others=>'0');
 51     
 52 end architecture;

You can find the rom model and testbench here and memory_list file here.

  1 -------------------------------------------------------
  2 -- Design Name : rom_using_case
  3 -- File Name   : rom_using_case.vhd
  4 -- Function    : ROM using case
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10     use ieee.std_logic_unsigned.all;
 11     use ieee.std_logic_arith.all;
 12 
 13 entity rom_using_case is
 14     port (
 15         ce      :in  std_logic;                    -- Chip Enable
 16         read_en :in  std_logic;                    -- Read Enable
 17         address :in  std_logic_vector (3 downto 0);-- Address input
 18         data    :out std_logic_vector (7 downto 0) -- Data output
 19     );
 20 end entity;
 21 architecture behavior of rom_using_case is
 22 
 23 begin
 24        
 25     process (read_en, address) begin
 26         if (read_en = '1') then
 27             case (address) is
 28                 when x"0"   => data <= conv_std_logic_vector(10,8);
 29                 when x"1"   => data <= conv_std_logic_vector(55,8);
 30                 when x"2"   => data <= conv_std_logic_vector(244,8);
 31                 when x"3"   => data <= (others=>'0');
 32                 when x"4"   => data <= conv_std_logic_vector(1,8);
 33                 when x"5"   => data <= x"ff";
 34                 when x"6"   => data <= x"11";
 35                 when x"7"   => data <= x"01";
 36                 when x"8"   => data <= x"10";
 37                 when x"9"   => data <= x"00";
 38                 when x"A"   => data <= x"10";
 39                 when x"B"   => data <= x"15";
 40                 when x"C"   => data <= x"60";
 41                 when x"D"   => data <= x"90";
 42                 when x"E"   => data <= x"70";
 43                 when x"F"   => data <= x"90";
 44                 when others => data <= x"00";
 45             end case;
 46         end if;
 47     end process;
 48 
 49 end architecture;

  1 -------------------------------------------------------
  2 -- Design Name : rom_using_constant
  3 -- File Name   : rom_using_constant.vhd
  4 -- Function    : ROM using constant
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10     use ieee.std_logic_unsigned.all;
 11     use ieee.std_logic_arith.all;
 12 
 13 entity rom_using_constant is
 14     port (
 15         read_en :in  std_logic;                    -- Read Enable
 16         address :in  std_logic_vector (3 downto 0);-- Address input
 17         data    :out std_logic_vector (7 downto 0) -- Data output
 18     );
 19 end entity;
 20 architecture behavior of rom_using_constant is
 21     subtype ROM_Word is std_logic_vector (7 downto 0);
 22     subtype ROM_Addr is integer range 0 to 15;
 23     
 24     type ROM is array (ROM_Addr) of ROM_Word;
 25 
 26     constant ROM_Table :ROM := (
 27         conv_std_logic_vector(10,8),
 28         conv_std_logic_vector(55,8),
 29         conv_std_logic_vector(244,8),
 30         "00000000",
 31         conv_std_logic_vector(1,8),
 32         x"ff",
 33         x"11",
 34         x"01",
 35         x"10",
 36         x"00",
 37         x"10",
 38         x"15",
 39         x"60",
 40         x"70",
 41         x"90",
 42         x"00");
 43     
 44 begin
 45        
 46     process (read_en, address) begin
 47         if (read_en = '1') then
 48             data <= ROM_Table(conv_integer(address));
 49         end if;
 50     end process;
 51 
 52 end architecture;
 53 
 54 

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Deepak Kumar Tala - All rights reserved

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