1 -------------------------------------------------------
  2 -- Design Name : ram_sp_sr_sw
  3 -- File Name   : ram_sp_sr_sw.vhd
  4 -- Function    : Synchronous read write RAM 
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10     use ieee.std_logic_unsigned.all;
 11 
 12 entity ram_sp_ar_sw is
 13     generic (
 14         DATA_WIDTH :integer := 8;
 15         ADDR_WIDTH :integer := 8
 16     );
 17     port (
 18         clk     :in    std_logic;                                -- Clock Input
 19         address :in    std_logic_vector (ADDR_WIDTH-1 downto 0); -- address Input
 20         data    :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data bi-directional
 21         cs      :in    std_logic;                                -- Chip Select
 22         we      :in    std_logic;                                -- Write Enable/Read Enable
 23         oe      :in    std_logic                                 -- Output Enable
 24 
 25     );
 26 end entity;
 27 architecture rtl of ram_sp_ar_sw is
 28    ----------------Internal variables----------------
 29     constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
 30 
 31     signal data_out :std_logic_vector (DATA_WIDTH-1 downto 0);
 32 
 33     type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
 34     signal mem : RAM (0 to RAM_DEPTH-1);
 35 begin
 36 
 37    ----------------Code Starts Here------------------
 38    -- Tri-State Buffer control
 39    -- output : When we = 0, oe = 1, cs = 1
 40     data <= data_out when (cs = '1' and oe = '1' and we = '0') else (others=>'Z');
 41 
 42    -- Memory Write Block
 43    -- Write Operation : When we = 1, cs = 1
 44     MEM_WRITE:
 45     process (clk) begin
 46         if (rising_edge(clk)) then
 47             if (cs = '1' and we = '1') then
 48                 mem(conv_integer(address)) <= data;
 49             end if;
 50         end if;
 51     end process;
 52 
 53    -- Memory Read Block
 54    -- Read Operation : When we = 0, oe = 1, cs = 1
 55     MEM_READ:
 56     process (clk) begin
 57         if (rising_edge(clk)) then
 58             if (cs = '1' and we = '0' and oe = '1') then
 59                  data_out <= mem(conv_integer(address));
 60             end if;
 61         end if;
 62     end process;
 63 
 64 end architecture;

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