1 -------------------------------------------------------
  2 -- Design Name : mux_using_with
  3 -- File Name   : mux_using_with.vhd
  4 -- Function    : 2:1 Mux using with-select
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity mux_using_with is
 12     port (
 13         din_0   :in  std_logic;-- Mux first input
 14         din_1   :in  std_logic;-- Mux Second input
 15         sel     :in  std_logic;-- Select input
 16         mux_out :out std_logic -- Mux output
 17 
 18     );
 19 end entity;
 20 
 21 architecture behavior of mux_using_with is
 22 
 23 begin
 24     with (sel) select
 25     mux_out <= din_0 when '0',
 26                din_1 when others;
 27         
 28 end architecture;

  1 -------------------------------------------------------
  2 -- Design Name : mux_using_when
  3 -- File Name   : mux_using_assign.v
  4 -- Function    : 2:1 Mux using when
  5 -- Coder       : Deepak Kumar Tala
  6 -------------------------------------------------------
  7 library ieee;
  8     use ieee.std_logic_1164.all;
  9 
 10 entity mux_using_when is
 11     port (
 12         din_0   :in  std_logic;-- Mux first input
 13         din_1   :in  std_logic;-- Mux Second input
 14         sel     :in  std_logic;-- Select input
 15         mux_out :out std_logic -- Mux output
 16 
 17     );
 18 end entity;
 19 
 20 architecture behavior of mux_using_when is
 21 
 22 begin
 23     mux_out <= din_0 when (sel = '0') else
 24                din_1;
 25         
 26 end architecture;

  1 -------------------------------------------------------
  2 -- Design Name : mux_using_if
  3 -- File Name   : mux_using_if.vhd
  4 -- Function    : 2:1 Mux using If
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity mux_using_if is
 12     port (
 13         din_0   :in  std_logic;-- Mux first input
 14         din_1   :in  std_logic;-- Mux Second input
 15         sel     :in  std_logic;-- Select input
 16         mux_out :out std_logic -- Mux output
 17 
 18     );
 19 end entity;
 20 
 21 architecture behavior of mux_using_if is
 22 
 23 begin
 24     MUX:
 25     process (sel, din_0, din_1) begin
 26         if (sel = '0') then
 27             mux_out <= din_0;
 28         else
 29             mux_out <= din_1;
 30         end if;
 31     end process;
 32 end architecture;

  1 -------------------------------------------------------
  2 -- Design Name : mux_using_case
  3 -- File Name   : mux_using_case.vhd
  4 -- Function    : 2:1 Mux using Case
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity mux_using_case is
 12     port (
 13         din_0   :in  std_logic;-- Mux first input
 14         din_1   :in  std_logic;-- Mux Second input
 15         sel     :in  std_logic;-- Select input
 16         mux_out :out std_logic -- Mux output
 17 
 18     );
 19 end entity;
 20 
 21 architecture behavior of mux_using_case is
 22 
 23 begin
 24     MUX:
 25     process (sel, din_0, din_1) begin
 26         case sel is
 27             when '0'    => mux_out <= din_0;
 28             when others => mux_out <= din_1;
 29         end case;
 30     end process;
 31 end architecture;

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