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Random Counter (LFSR)
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1 -------------------------------------------------------
2 -- Design Name : lfsr
3 -- File Name : lfsr.vhd
4 -- Function : Linear feedback shift register
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7 -------------------------------------------------------
8 library ieee;
9 use ieee.std_logic_1164.all;
10
11 entity lfsr is
12 port (
13 cout :out std_logic_vector (7 downto 0); 14 enable :in std_logic; -- Enable counting
15 clk :in std_logic; -- Input rlock
16 reset :in std_logic -- Input reset
17 );
18 end entity;
19
20 architecture rtl of lfsr is
21 signal count :std_logic_vector (7 downto 0);
22 signal linear_feedback :std_logic;
23
24 begin
25 linear_feedback <= not(count(7) xor count(3));
26
27
28 process (clk, reset) begin
29 if (reset = '1') then
30 count <= (others=>'0');
31 elsif (rising_edge(clk)) then
32 if (enable = '1') then
33 count <= (count(6) & count(5) & count(4) & count(3)
34 & count(2) & count(1) & count(0) &
35 linear_feedback);
36 end if;
37 end if;
38 end process;
39 cout <= count;
40 end architecture;
You could download file vhdl_examples here
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LFSR Up/Down
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1 -------------------------------------------------------
2 -- Design Name : lfsr
3 -- File Name : lfsr_updown.vhd
4 -- Function : Linear feedback shift register
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7 -------------------------------------------------------
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_unsigned.all;
11
12 entity lfsr_updown is
13 generic (
14 WIDTH :integer := 8
15 );
16 port (
17 clk :in std_logic; -- Clock input
18 reset :in std_logic; -- Reset input
19 enable :in std_logic; -- Enable input
20 up_down :in std_logic; -- Up Down input
21 count :out std_logic_vector (WIDTH-1 downto 0); -- Count output
22 overflow :out std_logic -- Overflow output
23 );
24 end entity;
25
26 architecture rtl of lfsr_updown is
27 signal cnt :std_logic_vector (WIDTH-1 downto 0);
28 begin
29
30 process (up_down, cnt) begin
31 if ((up_down = '1' and cnt = 1) or
32 (up_down = '0' and (cnt(WIDTH-1) = '1' and
33 cnt(WIDTH-2 downto 0) = 0))) then
34 overflow <= '1';
35 else
36 overflow <= '0';
37 end if;
38 end process;
39
40 process (clk, reset, cnt, enable, up_down)
41 variable temp_a :std_logic_vector (WIDTH-1 downto 0);
42 variable temp_b :std_logic :='1';
43 begin
44
45 temp_a := cnt and "01100011";
46 temp_b :='1';
47 for i in 0 to WIDTH-1 loop
48 temp_b := temp_a(i) xnor temp_b;
49 end loop;
50
51 if (rising_edge(clk)) then
52 if (reset = '1') then
53 cnt <= (others=>'0');
54 elsif (enable = '1') then
55 if (up_down = '1') then
56 cnt <= (temp_b & cnt(WIDTH-1 downto 1));
57 else
58 cnt <= (cnt(WIDTH-2 downto 0) & temp_b);
59 end if;
60 end if;
61 end if;
62 end process;
63 count <= cnt;
64
65 end architecture;
You could download file vhdl_examples here
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1 -------------------------------------------------------
2 -- Design Name : lfsr
3 -- File Name : lfsr_updown_tb.vhd
4 -- Function : Linear feedback shift register
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7 -------------------------------------------------------
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_textio.all;
11 use std.textio.all;
12
13 entity lfsr_updown_tb is
14 end entity;
15 architecture test of lfsr_updown_tb is
16
17 constant WIDTH :integer := 8;
18
19 signal clk :std_logic := '0';
20 signal reset :std_logic := '1';
21 signal enable :std_logic := '0';
22 signal up_down :std_logic := '0';
23 signal count :std_logic_vector (WIDTH-1 downto 0);
24 signal overflow :std_logic;
25
26 component lfsr_updown is
27 generic (
28 WIDTH :integer := 8
29 );
30 port (
31 clk :in std_logic; -- Clock input
32 reset :in std_logic; -- Reset input
33 enable :in std_logic; -- Enable input
34 up_down :in std_logic; -- Up Down input
35 count :out std_logic_vector (WIDTH-1 downto 0); -- Count output
36 overflow :out std_logic -- Overflow output
37 );
38 end component;
39
40 constant PERIOD :time := 20 ns;
41
42 begin
43 clk <= not clk after PERIOD/2;
44 reset <= '0' after PERIOD*10;
45 enable <= '1' after PERIOD*11;
46 up_down <= '1' after PERIOD*22;
47
48 -- Display the time and result
49 process (reset, enable, up_down, count, overflow)
50 variable wrbuf :line;
51 begin
52 write(wrbuf, string'("Time: " )); write(wrbuf, now);
53 write(wrbuf, string'(" rst: " )); write(wrbuf, reset);
54 write(wrbuf, string'(" enable: " )); write(wrbuf, enable);
55 write(wrbuf, string'(" up_down: " )); write(wrbuf, up_down);
56 write(wrbuf, string'(" count: " )); write(wrbuf, count);
57 write(wrbuf, string'(" overflow: ")); write(wrbuf, overflow);
58 writeline(output, wrbuf);
59 end process;
60
61 Inst_lfsr_updown : lfsr_updown
62 port map (
63 clk => clk,
64 reset => reset,
65 enable => enable,
66 up_down => up_down,
67 count => count,
68 overflow => overflow
69 );
70
71 end architecture;
You could download file vhdl_examples here
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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