1 -------------------------------------------------------
  2 -- Design Name : dff_async_reset
  3 -- File Name   : dff_async_reset.vhd
  4 -- Function    : D flip-flop async reset
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity dff_async_reset is
 12     port (
 13         data  :in  std_logic;-- Data input
 14         clk   :in  std_logic;-- Clock input
 15         reset :in  std_logic;-- Reset input
 16         q     :out std_logic -- Q output
 17 
 18     );
 19 end entity;
 20 
 21 architecture rtl of dff_async_reset is
 22 
 23 begin
 24     process (clk, reset) begin
 25         if (reset = '0') then
 26             q <= '0';
 27         elsif (rising_edge(clk)) then
 28             q <= data;
 29         end if;
 30     end process;
 31 
 32 end architecture;

  1 -------------------------------------------------------
  2 -- Design Name : dff_sync_reset
  3 -- File Name   : dff_sync_reset.vhd
  4 -- Function    : D flip-flop sync reset
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity dff_sync_reset is
 12     port (
 13         data  :in  std_logic;-- Data input
 14         clk   :in  std_logic;-- Clock input
 15         reset :in  std_logic;-- Reset input
 16         q     :out std_logic -- Q output
 17 
 18     );
 19 end entity;
 20 
 21 architecture rtl of dff_sync_reset is
 22 
 23 begin
 24     process (clk) begin
 25         if (rising_edge(clk)) then
 26             if (reset = '0') then
 27                 q <= '0';
 28             else
 29                 q <= data;
 30             end if;
 31         end if;
 32     end process;
 33 
 34 end architecture;

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