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Single Port RAM Asynch Read, Synch Write
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1 //===========================================
2 // Function : Asynchronous read write RAM
3 // Coder : Deepak Kumar Tala
4 // Date : 1-Nov-2005
5 //===========================================
6 module ram_sp_ar_sw #(parameter DATA_WIDTH = 8,
7 parameter ADDR_WIDTH = 8,
8 parameter RAM_DEPTH = (1 << ADDR_WIDTH))(
9 input wire clk , // Clock Input
10 input wire [ADDR_WIDTH-1:0] address , // Address Input
11 inout wire [DATA_WIDTH-1:0] data , // Data bi-directional
12 input wire cs , // Chip Select
13 input wire we , // Write Enable/Read Enable
14 input wire oe // Output Enable
15 );
16 //--------------Internal variables----------------
17 reg [DATA_WIDTH-1:0] data_out ;
18 // Use Associative array to save memory footprint
19 typedef reg [ADDR_WIDTH-1:0] mem_addr;
20 reg [DATA_WIDTH-1:0] mem [mem_addr];
21 //--------------Code Starts Here------------------
22 // Tri-State Buffer control
23 // output : When we = 0, oe = 1, cs = 1
24 assign data = (cs && oe && ! we) ? data_out : 8'bz;
25 // Memory Write Block
26 // Write Operation : When we = 1, cs = 1
27 always @ (posedge clk)
28 begin : MEM_WRITE
29 if ( cs && we ) begin
30 mem[address] = data;
31 end
32 end
33 // Memory Read Block
34 // Read Operation : When we = 0, oe = 1, cs = 1
35 always @ (address or cs or we or oe)
36 begin : MEM_READ
37 if (cs && ! we && oe) begin
38 data_out = mem[address];
39 end
40 end
41
42 endmodule // End of Module ram_sp_ar_sw
You could download file sv_examples here
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
Do you have any Comment? mail me at:deepak@asic-world.com
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