1 //===========================================
  2 // Function : Asynchronous read write RAM
  3 // Coder    : Deepak Kumar Tala
  4 // Date     : 1-Nov-2005
  5 //===========================================
  6 module ram_dp_ar_aw #(parameter DATA_WIDTH = 8,
  7                       parameter ADDR_WIDTH = 8,
  8                       parameter RAM_DEPTH = (1 << ADDR_WIDTH))(
  9 input  wire [ADDR_WIDTH-1:0] address_0 , // address_0 Input
 10 inout  wire [DATA_WIDTH-1:0] data_0    , // data_0 bi-directional
 11 input  wire                  cs_0      , // Chip Select
 12 input  wire                  we_0      , // Write Enable/Read Enable
 13 input  wire                  oe_0      , // Output Enable
 14 input  wire [ADDR_WIDTH-1:0] address_1 , // address_1 Input
 15 inout  wire [DATA_WIDTH-1:0] data_1    , // data_1 bi-directional
 16 input  wire                  cs_1      , // Chip Select
 17 input  wire                  we_1      , // Write Enable/Read Enable
 18 input  wire                  oe_1        // Output Enable
 19 ); 
 20 //--------------Internal variables---------------- 
 21 reg [DATA_WIDTH-1:0] data_0_out ; 
 22 reg [DATA_WIDTH-1:0] data_1_out ;
 23 // Use Associative array to save memory footprint
 24 typedef reg [ADDR_WIDTH-1:0] mem_addr;
 25 reg [DATA_WIDTH-1:0] mem [mem_addr];
 26 
 27 //--------------Code Starts Here------------------ 
 28 // Memory Write Block 
 29 // Write Operation : When we_0 = 1, cs_0 = 1
 30 always_latch 
 31 begin : MEM_WRITE
 32   if ( cs_0 && we_0 ) begin
 33      mem[address_0] = data_0;
 34   end else if  (cs_1 && we_1) begin
 35      mem[address_1] = data_1;
 36   end
 37 end
 38 
 39 // Tri-State Buffer control 
 40 // output : When we_0 = 0, oe_0 = 1, cs_0 = 1
 41 assign data_0 = (cs_0 && oe_0 &&  ! we_0) ? data_0_out : 8'bz; 
 42 
 43 // Memory Read Block 
 44 // Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 1
 45 always_comb
 46 begin : MEM_READ_0
 47   if (cs_0 &&  ! we_0 && oe_0) begin
 48     data_0_out = mem[address_0]; 
 49   end else begin
 50     data_0_out = 0; 
 51   end
 52 end 
 53 
 54 //Second Port of RAM
 55 // Tri-State Buffer control 
 56 // output : When we_0 = 0, oe_0 = 1, cs_0 = 1
 57 assign data_1 = (cs_1 && oe_1 &&  ! we_1) ? data_1_out : 8'bz; 
 58 // Memory Read Block 1 
 59 // Read Operation : When we_1 = 0, oe_1 = 1, cs_1 = 1
 60 always_latch
 61 begin : MEM_READ_1
 62   if (cs_1 &&  ! we_1 && oe_1) begin
 63     data_1_out = mem[address_1]; 
 64   end else begin
 65     data_1_out = 0; 
 66   end
 67 end
 68 
 69 endmodule // End of Module ram_dp_ar_aw

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