|
|
|
|
|
|
|
|
|
|
|
|
Mux : Using assign Statement
|
|
|
|
|
|
1 //-----------------------------------------------------
2 // Design Name : mux_using_assign
3 // File Name : mux_using_assign.sv
4 // Function : 2:1 Mux using Assign
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module mux_using_assign (
8 input wire din_0 , // Mux first input
9 input wire din_1 , // Mux Second input
10 input wire sel , // Select input
11 output wire mux_out // Mux output
12 );
13 //-------------Code Start-----------------
14 assign mux_out = (sel) ? din_1 : din_0;
15
16 endmodule //End Of Module mux
You could download file sv_examples here
|
|
|
|
|
|
|
|
|
|
|
|
Mux : Using if Statement
|
|
|
|
|
|
1 //-----------------------------------------------------
2 // Design Name : mux_using_if
3 // File Name : mux_using_if.sv
4 // Function : 2:1 Mux using If
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module mux_using_if(
8 input wire din_0 , // Mux first input
9 input wire din_1 , // Mux Second input
10 input wire sel , // Select input
11 output reg mux_out // Mux output
12 );
13 //-------------Code Starts Here---------
14 always_comb
15 begin : MUX
16 if (sel == 1'b0) begin
17 mux_out = din_0;
18 end else begin
19 mux_out = din_1 ;
20 end
21 end
22
23 endmodule //End Of Module mux
You could download file sv_examples here
|
|
|
|
|
|
Mux : Using case Statement
|
|
|
|
|
|
1 //-----------------------------------------------------
2 // Design Name : mux_using_case
3 // File Name : mux_using_case.sv
4 // Function : 2:1 Mux using Case
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 module mux_using_case(
8 input wire din_0 , // Mux first input
9 input wire din_1 , // Mux Second input
10 input wire sel , // Select input
11 output reg mux_out // Mux output
12 );
13 //-------------Code Starts Here---------
14 always @ (*)
15 MUX : begin
16 case (sel)
17 1'b0 : mux_out = din_0;
18 1'b1 : mux_out = din_1;
19 endcase
20 end
21
22 endmodule //End Of Module mux
You could download file sv_examples here
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
Do you have any Comment? mail me at:deepak@asic-world.com
|
|
|