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FIFO Scoreboard
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1 class fifo_sb;
2 mailbox fifo = new();
3 integer size;
4
5 function new();
6 begin
7 size = 0;
8 end
9 endfunction
10
11 task addItem(bit [7:0] data);
12 begin
13 if (size == 7) begin
14 $write("%dns : ERROR : Over flow detected, current occupancy %d\n",
15 $time, size);
16 end else begin
17 fifo.put(data);
18 size ++;
19 end
20 end
21 endtask
22
23 task compareItem (bit [7:0] data);
24 begin
25 bit [7:0] cdata = 0;
26 if (size == 0) begin
27 $write("%dns : ERROR : Under flow detected\n", $time);
28 end else begin
29 fifo.get (cdata);
30 if (data ! = cdata) begin
31 $write("%dns : ERROR : Data mismatch, Expected %x Got %x\n",
32 $time, cdata, data );
33 end
34 size --;
35 end
36 end
37 endtask
38 endclass
You could download file sv_examples here
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FIFO Driver
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1 class fifo_driver;
2 fifo_sb sb;
3 virtual fifo_ports ports;
4 virtual fifo_monitor_ports mports;
5
6 bit rdDone;
7 bit wrDone;
8
9 integer wr_cmds;
10 integer rd_cmds;
11
12 function new (virtual fifo_ports ports, virtual fifo_monitor_ports mports);
13 begin
14 this.ports = ports;
15 this.mports = mports;
16 sb = new();
17 wr_cmds = 5;
18 rd_cmds = 5;
19 rdDone = 0;
20 wrDone = 0;
21 ports.wr_cs = 0;
22 ports.rd_cs = 0;
23 ports.wr_en = 0;
24 ports.rd_en = 0;
25 ports.data_in = 0;
26 end
27 endfunction
28
29 task monitorPush();
30 begin
31 bit [7:0] data = 0;
32 while (1) begin
33 @ (posedge mports.clk);
34 if (mports.wr_cs== 1 && mports.wr_en== 1) begin
35 data = mports.data_in;
36 sb.addItem(data);
37 $write("%dns : Write posting to scoreboard data = %x\n",$time, data);
38 end
39 end
40 end
41 endtask
42
43 task monitorPop();
44 begin
45 bit [7:0] data = 0;
46 while (1) begin
47 @ (posedge mports.clk);
48 if (mports.rd_cs== 1 && mports.rd_en== 1) begin
49 data = mports.data_out;
50 $write("%dns : Read posting to scoreboard data = %x\n",$time, data);
51 sb.compareItem(data);
52 end
53 end
54 end
55 endtask
56
57 task go();
58 begin
59 // Assert reset first
60 reset();
61 // Start the monitors
62 repeat (5) @ (posedge ports.clk);
63 $write("%dns : Starting Pop and Push monitors\n",$time);
64 fork
65 monitorPop();
66 monitorPush();
67 join_none
68 $write("%dns : Starting Pop and Push generators\n",$time);
69 fork
70 genPush();
71 genPop();
72 join_none
73
74 while ( ! rdDone && ! wrDone) begin
75 @ (posedge ports.clk);
76 end
77 repeat (10) @ (posedge ports.clk);
78 $write("%dns : Terminating simulations\n",$time);
79 end
80 endtask
81
82 task reset();
83 begin
84 repeat (5) @ (posedge ports.clk);
85 $write("%dns : Asserting reset\n",$time);
86 ports.rst= 1'b1;
87 // Init all variables
88 rdDone = 0;
89 wrDone = 0;
90 repeat (5) @ (posedge ports.clk);
91 ports.rst= 1'b0;
92 $write("%dns : Done asserting reset\n",$time);
93 end
94 endtask
95
96 task genPush();
97 begin
98 bit [7:0] data = 0;
99 integer i = 0;
100 for ( i = 0; i < wr_cmds; i++) begin
101 data = $random();
102 @ (posedge ports.clk);
103 while (ports.full== 1'b1) begin
104 ports.wr_cs = 1'b0;
105 ports.wr_en = 1'b0;
106 ports.data_in= 8'b0;
107 @ (posedge ports.clk);
108 end
109 ports.wr_cs = 1'b1;
110 ports.wr_en = 1'b1;
111 ports.data_in= data;
112 end
113 @ (posedge ports.clk);
114 ports.wr_cs = 1'b0;
115 ports.wr_en = 1'b0;
116 ports.data_in= 8'b0;
117 repeat (10) @ (posedge ports.clk);
118 wrDone = 1;
119 end
120 endtask
121
122 task genPop();
123 begin
124 integer i = 0;
125 for ( i = 0; i < rd_cmds; i++) begin
126 @ (posedge ports.clk);
127 while (ports.empty== 1'b1) begin
128 ports.rd_cs = 1'b0;
129 ports.rd_en = 1'b0;
130 @ (posedge ports.clk);
131 end
132 ports.rd_cs = 1'b1;
133 ports.rd_en = 1'b1;
134 end
135 @ (posedge ports.clk);
136 ports.rd_cs = 1'b0;
137 ports.rd_en = 1'b0;
138 repeat (10) @ (posedge ports.clk);
139 rdDone = 1;
140 end
141 endtask
142 endclass
You could download file sv_examples here
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Ports File
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1 `ifndef FIFO_PORTS_SV
2 `define FIFO_PORTS_SV
3
4 interface fifo_ports (
5 input wire clk ,
6 output logic rst ,
7 input wire full ,
8 input wire empty ,
9 output logic wr_cs ,
10 output logic rd_cs ,
11 output logic rd_en ,
12 output logic wr_en ,
13 output logic [7:0] data_in ,
14 input wire [7:0] data_out
15 );
16 endinterface
17
18
19 interface fifo_monitor_ports (
20 input wire clk ,
21 input wire rst ,
22 input wire full ,
23 input wire empty ,
24 input wire wr_cs ,
25 input wire rd_cs ,
26 input wire rd_en ,
27 input wire wr_en ,
28 input wire [7:0] data_in ,
29 input wire [7:0] data_out
30 );
31 endinterface
32
33
34 `endif
You could download file sv_examples here
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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