1 //-----------------------------------------------------
  2 // Design Name : cam
  3 // File Name   : cam.v
  4 // Function    : CAM
  5 // Coder      : Deepak
  6 //-----------------------------------------------------
  7 module cam (
  8 clk         , // Cam clock
  9 cam_enable  , // Cam enable
 10 cam_data_in , // Cam data to match
 11 cam_hit_out , // Cam match has happened
 12 cam_addr_out  // Cam output address 
 13 );
 14 
 15 parameter ADDR_WIDTH  = 8;
 16 parameter DEPTH       = 1 << ADDR_WIDTH;
 17 //------------Input Ports--------------
 18 input                    clk;      
 19 input                    cam_enable;   
 20 input  [DEPTH-1:0]       cam_data_in;  
 21 //----------Output Ports--------------
 22 output                   cam_hit_out;  
 23 output [ADDR_WIDTH-1:0]  cam_addr_out;  
 24 //------------Internal Variables--------
 25 reg [ADDR_WIDTH-1:0]  cam_addr_out;
 26 reg                   cam_hit_out;
 27 reg [ADDR_WIDTH-1:0]  cam_addr_combo;
 28 reg                   cam_hit_combo;
 29 reg                   found_match;
 30 integer               i;
 31 //-------------Code Starts Here-------
 32 always @(cam_data_in) begin
 33   cam_addr_combo   = {ADDR_WIDTH{1'b0}};
 34   found_match      = 1'b0;
 35   cam_hit_combo    = 1'b0;
 36   for (i=0; i<DEPTH; i=i+1) begin
 37     if (cam_data_in[i] &&  ! found_match) begin
 38       found_match     = 1'b1;
 39       cam_hit_combo   = 1'b1;
 40       cam_addr_combo  = i;
 41     end else begin
 42       found_match     = found_match;
 43       cam_hit_combo   = cam_hit_combo;
 44       cam_addr_combo  = cam_addr_combo;
 45     end
 46   end
 47 end
 48 
 49 // Register the outputs 
 50 always @(posedge clk) begin
 51   if (cam_enable) begin
 52     cam_hit_out  <=  cam_hit_combo;
 53     cam_addr_out <=  cam_addr_combo;
 54   end else begin
 55     cam_hit_out  <=  1'b0;
 56     cam_addr_out <=  {ADDR_WIDTH{1'b0}};
 57   end
 58 end
 59 
 60 endmodule 

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Deepak Kumar Tala - All rights reserved

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