1 module memory(
  2 address,
  3 data_in,
  4 data_out,
  5 read_write,
  6 chip_en
  7 );
  8 
  9 input [7:0] address, data_in;
 10 output [7:0] data_out;
 11 input read_write, chip_en;
 12 
 13 reg [7:0] mem [0:255];
 14 
 15 always @ (address or data_in or read_write or chip_en)
 16 if (read_write == 1 && chip_en == 1) begin
 17   mem[address] = data_in;
 18 end
 19 
 20 assign data_out = (read_write == 0 && chip_en == 1) ? mem[address] : 0;
 21 
 22 endmodule

  1 `include "memory.v"
  2 module memory_tb();
  3 
  4 reg [7:0] address, data_in;
  5 wire [7:0] data_out;
  6 reg  read_write, chip_en;
  7 reg clk;
  8 
  9 initial begin
 10   $dumpfile("memory.vcd");
 11   $dumpvars();
 12   clk = 0;
 13   read_write = 0;
 14   chip_en = 0;
 15 end	
 16 
 17 always  #5  clk = ~clk;
 18 
 19 memory U_memory(
 20 .address             (address),
 21 .data_in             (data_in),
 22 .data_out            (data_out),
 23 .read_write          (read_write),
 24 .chip_en             (chip_en)
 25 );
 26 endmodule

  1 <'
  2 import mem_base_object;
  3 import mem_driver;
  4 import mem_scoreboard;
  5 import mem_ip_monitor;
  6 import mem_op_monitor;
  7 import mem_txgen;
  8 
  9 struct mem_tb_top {
 10   mem_driver     : mem_driver;
 11   mem_scoreboard : mem_scoreboard;
 12   
 13   mem_txgen      : mem_txgen;
 14     keep mem_txgen.mem_driver == mem_driver;
 15   mem_ip_monitor : mem_ip_monitor;
 16     keep mem_ip_monitor.mem_scoreboard == mem_scoreboard;
 17   mem_op_monitor : mem_op_monitor;
 18     keep mem_op_monitor.mem_scoreboard == mem_scoreboard;
 19 
 20   event clk is rise('memory_tb.clk') @sim;
 21 
 22   start_tb()@clk is {
 23     start mem_ip_monitor.input_monitor();
 24     start mem_op_monitor.output_monitor();
 25     mem_txgen.gen_cmds();
 26     stop_run();
 27   };
 28 };
 29 
 30 extend sys {
 31   tb : mem_tb_top;
 32   run() is also {
 33     start tb.start_tb();
 34   };
 35 };
 36 '>

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com