|
|
|
|
|
|
|
|
|
|
|
|
Why ?
|
|
|
|
|
|
There just isn't a great source of detailed VLSI/DIGITAL information out there. If I actually keep this up, this should be it. However, unless people take an active interest and submit some ideas, tutorials, examples, may be some cores etc., it may die very soon. So, please let me know what you think and what you're working on. I'd love to post people's contributions. |
|
|
|
|
|
What's On the Site ?
|
|
|
|
|
|
First, look to the left. This is really a site for ASIC/DIGITAL beginners. My interests run mainly to digital design and how to apply that to ASIC/FPGA/Board design and how to verify them. So there is a definite bias towards that on this site. However, I would be very pleased to post information concerning embedded systems, analog design, VLSI. You have to tell me. |
|
|
|
|
|
The Future...
|
|
|
|
|
|
While only some of the sections on this site have useful or interesting things at the moment, I hope that they will fill out quickly. Provided I get some positive response, things should be added on a regular basis. Also, I'd like to set up a Frequently asked questions for all the sections...may be trying something new.. ..time will decide. |
|
|
|
|
|
Me
|
|
|
|
|
|
My name is Deepak Kumar Tala, I am Managing Director of SmartDV Technologies India Private Limited, with more than 13 years design and Verification experience in ASIC/Board/FPGA/Emulation. |
|
|
|
|
|
Using information in this web page ?
|
|
|
|
|
|
You can freely use the content of this webpage without any restrictions provided you point to www.asic-world.com as your reference source. However I don't give persmission to rehost any content of this website. |
|
|
|
|
|
What's New ?
|
|
|
|
|
|
Completed writing of AOP,VMM and functional coverage chapter in Systemverilog. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
Do you have any Comment? mail me at:deepak@asic-world.com
|
|